Device mismatch in a neuromorphic system implements random features for regression

Richter, Ole; Reinhart, René Felix; Nease, Stephen; Steil, Jochen J.; Chicca, Elisabetta

doi:10.1109/biocas.2015.7348416

Cited by 13 publications

(7 citation statements)

References 16 publications

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“…Examples of theoretical neural processing frameworks that require variability can be found in the domain of ensemble learning 53 , reservoir computing 54 and liquid state machines 55 . Current efforts in neuromorphic engineering for implementing such frameworks to solve spatio-temporal pattern recognition problems rely on the variability provided by transistor device-mismatch effects [56][57][58][59][60] . Integration of memristive devices with inhomogeneous properties in such architectures can provide a richer set of distributions useful for enhancing the computational abilities of these networks.…”

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confidence: 99%

A recipe for creating ideal hybrid memristive-CMOS neuromorphic processing systems

Chicca

Indiveri

2020

Applied Physics Letters

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The development of memristive device technologies has reached a level of maturity to enable the design of complex and large-scale hybrid memristive-CMOS neural processing systems. These systems offer promising solutions for implementing novel in-memory computing architectures for machine learning and data analysis problems. We argue that they are also ideal building blocks for the integration in neuromorphic electronic circuits suitable for ultra-low power brain-inspired sensory processing systems, therefore leading to the innovative solutions for always-on edge-computing and Internet-of-Things (IoT) applications. Here we present a recipe for creating such systems based on design strategies and computing principles inspired by those used in mammalian brains. We enumerate the specifications and properties of memristive devices required to support always-on learning in neuromorphic computing system and to minimize their power consumption. Finally, we discuss in what cases such neuromorphic systems can complement conventional processing ones and highlight the importance of exploiting the physics of both the memristive devices and of the CMOS circuits interfaced to them.Neuromorphic computing has recently received considerable attention as a discipline that can offer promising technological solutions for implementing power-and size-efficient sensory-processing, learning, and Artificial Intelligence (AI) applications 1-5 , especially in cases in which the computing system has to operate autonomously "at the edge", i.e., without having to connect to powerful (but power hungry) server farms in the "cloud". The term "neuromorphic" was originally coined in the early 90's by Carver Mead to refer to mixed signal analog/digital Very Large Scale Integration (VLSI) computing systems based on the organizing principles used by the biological nervous systems 6 . In that context, "neuromorphic engineering" emerged as an interdisciplinary research field deeply rooted in biology that focused on building electronic neural processing systems by exploiting the physics of silicon to directly "emulate" the bio-physics of real neurons and synapses. More recently the definition of the term "neuromorphic" has been extended in two additional directions: on one hand to describe more generic spike-based processing systems engineered to "simulate" spiking neural networks for the exploration of large-scale computational neuroscience models 7-9 ; and on the other hand to describe dedicated electronic neural architectures that make use of both electronic Complementary Metal-Oxide Semiconductor (CMOS) circuits and memristive devices to implement neuron and synapse circuits 10,11 .Another recent and very promising trend in developing dedicated hardware architectures for building accelerated simulators of artificial neural networks is related to the field of machine learning and AI 12,13 . The types of neural networks being proposed within this context are only loosely inspired by biology, are aimed at high accuracy pattern recognition based on large...

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confidence: 99%

A recipe for creating ideal hybrid memristive-CMOS neuromorphic processing systems

Chicca

Indiveri

2020

Applied Physics Letters

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“…3. The spike-times of each of the lateral, delayed projections were independently drawn from a uniform 248 24, (25, 2), (45, 42), (28,57), (16,50) random distribution ranging from 1-50 ms before the direct forward excitation from A to B2, which defines the reference time (t = 0) of the pattern. All spike-patterns for which a given B2 neuron generated one or more postsynaptic spikes in response were accumulated to approximate the receptive field of that neuron.…”

Section: Mapping Of Receptive Fieldsmentioning

confidence: 99%

“…Learning and recognition of spatiotemporal patterns-in contrast to static spatial patterns, or even sequences of suchis a central conceptual problem to neuromorphic and eventbased processing [11], and has been addressed, for instance, with SNNs that incorporate neural signal-propagation delays [11]- [15]. Some current approaches to spatiotemporal pattern recognition with inhomogeneous neuromorphic hardware use neural processing frameworks that actually rely on variability in the processing elements [13], [16]- [21]-such as reservoir computing, liquid state machines, and ensemble learning. Another relevant concept is that of the Spiking Time-Difference Encoder (sTDE) [22], which provides a general neurocomputational primitive for temporal encoding but requires specialized hardware for its implementation.…”

Section: Introductionmentioning

confidence: 99%

Spatiotemporal Pattern Recognition in Single Mixed-Signal VLSI Neurons with Heterogeneous Dynamic Synapses

Nilsson,

Liwicki,

Sandin

2021

Preprint

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Realizing the potential of mixed-signal neuromorphic processors for ultra-low-power inference and learning requires efficient use of their inhomogeneous analog circuitry as well as sparse, time-based information encoding and processing. Here, we investigate spike-timing-based spatiotemporal receptive fields of output-neurons in the Spatiotemporal Correlator (STC) network, for which we used excitatory-inhibitory balanced disynaptic inputs instead of dedicated axonal or neuronal delays. We present hardware-in-the-loop experiments with a mixed-signal DYNAP-SE neuromorphic processor, in which five-dimensional receptive fields of hardware neurons were mapped by randomly sampling input spike-patterns from a uniform distribution. We find that, when the balanced disynaptic elements are randomly programmed, some of the neurons display distinct receptive fields. Furthermore, we demonstrate how a neuron was tuned to detect a particular spatiotemporal feature, to which it initially was nonselective, by activating a different subset of the inhomogeneous analog synaptic circuits. The energy dissipation of the balanced synaptic elements is one order of magnitude lower per lateral connection (0.65 nJ vs 9.3 nJ per spike) than former delaybased neuromorphic hardware implementations. Thus, we show how the inhomogeneous synaptic circuits could be utilized for resource-efficient implementation of STC network layers, in a way that enables synapse-address reprogramming as a discrete mechanism for feature tuning.

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“…In fact, the original neuromorphic definition by Carver Mead referred to analog circuits that operated in subthreshold mode [1]. There are a large variety of other neuromorphic analog implementations [7], [8], [12], [14], [17]- [19], [99], [100], [323], [324], [326]- [329], [331]- [333], [335]- [372], [374]- [387], [516], [571], [572], [578]- [580], [594]- [603], [606]- [610], [612]- [614], [620]- [640], [642]- [646], [648]- [653], [655]- [664], [666]- [683], [685]- [699], [701]- [703], [705]- [719], [722]- …”

Section: A High-levelmentioning

confidence: 99%

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

176

180

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Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture. This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems. The promise of the technology is to create a brainlike ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities. In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history. We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications. We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled. The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed.

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Device mismatch in a neuromorphic system implements random features for regression

Cited by 13 publications

References 16 publications

A recipe for creating ideal hybrid memristive-CMOS neuromorphic processing systems

A recipe for creating ideal hybrid memristive-CMOS neuromorphic processing systems

Spatiotemporal Pattern Recognition in Single Mixed-Signal VLSI Neurons with Heterogeneous Dynamic Synapses

A Survey of Neuromorphic Computing and Neural Networks in Hardware

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