Device Simulation Using Silvaco ATLAS Tool

Sarkar, Angsuman

doi:10.1201/b14860-6

Cited by 7 publications

(3 citation statements)

References 38 publications

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“…The mobility model was designed to work in conjunction with the defect density model of electronic states [29]. Physical models such as the IGZO.TOKYO temperature model, Shockley-Read-Hall (SRH) generation and recombination, and Fermi statistical model were used in the simulation process [30]. The ID-VD curve obtained from TCAD simulation showed a consistent trend with the experimental test results as a function of temperature.…”

Section: Resultsmentioning

confidence: 84%

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Wang,

Bi,

et al. 2024

Electronics

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The effect of high- and low-temperature conditions on the performance of IGZO TFT and logic circuits were investigated in this work. In the temperature range of 250−350 K, the performance of the IGZO TFT did not show significant changes and exhibited a certain degree of high- and low-temperature resistance. When the temperature was below 250 K, as the temperature decreased, the threshold voltage (VTH) of the IGZO TFT significantly increased, the field effect mobility (μFE) and the on state current (ION) significantly decreased. This is attributed to the lower excitation degree of charge carriers at extremely low temperatures, resulting in fewer charge carriers transitioning to the conduction or valence bands, and the formation of defects also limits carrier migration. When the temperature exceeded 350 K, as the temperature increased, more electrons could escape from the bandgap trap state and become free charge carriers, and the IGZO layer was thermally excited to produce more oxygen vacancies, resulting in higher μFE and lower VTH. In addition, the drain current noise spectral density of IGZO TFT conformed to the 1/ƒ noise characteristic, and the degradation mechanism of IGZO TFT over a wide temperature range was confirmed based on the changes in noise spectral density at different temperatures. In addition, an inverter logic unit circuit was designed based on IGZO TFT, and the performance changes over a wide temperature range were analyzed. This lays the foundation for IGZO TFT to be applied in integrated circuits with harsh environments.

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Section: Resultsmentioning

confidence: 84%

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Wang,

Bi,

et al. 2024

Electronics

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“…Physical models, such as Shockley-Reid-Hall (SRH) mechanisms, Auger and Langevin mechanisms of recombination, have been applied. In order to obtain the photon production rates along with the continuity equations, the solar spectra (AM1.5G) were imported into Atlas using the BEAM statement [8]. The change of current density versus voltage (J-V) under light was obtained, from which the main PV parameters were extracted, and Jsc, Voc, fill factor (FF), and PCE were calculated.…”

Section: Structure and Simulation Methodsmentioning

confidence: 99%

Optimization CIGS/CIGS Tandem Solar Cells by Adjusting Layer Thickness Using Silvaco-Tcad

Boroomandnasab,

Zolfaghari

2024

JGERI

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This research designed and simulated CIGS/CIGS back-to-back solar cells using Silvaco-Atlas software. We considered CIGS absorbing layer thickness and sub-cells as critical parameters to optimize the performance of the CIGS/CIGS tandem solar cell. The research comparatively examined the effect of different electrode metals, such as molybdenum, aluminum, titanium, and silver, on the efficiency. The electrical parameters of the best CIGS/CIGS tandem solar cell configuration were a short-circuit current density (Jsc) of 15.65 mA/cm², an open-circuit voltage (Voc) of 1.86 V, a fill factor (FF) of 86.04%, and a conversion efficiency (η) of 27.12%. The optimal CIGS absorbing layer thickness of the top and bottom cells corresponding to the maximum conversion efficiency obtained were 0.17 and 6.3 μm, respectively. In contrast, the optimal thickness of the Cds layer was 0.04 µm. Silver had the best performance in connecting layers between several metals. The results can be used to develop low-cost and high-efficiency solar cells.

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“…Here, the impact of the corner spacer on the DC performance of the JL MOSFET has been discussed in depth. SILVACO ATLAS [25][26] has been used for the device simulation. Hence, the proposed device-based digital logic circuits have been implemented and their DC performances are compared with the conventional JL MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mukherjee,

Ghosh,

Debnath

et al. 2024

JICS

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In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

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Device Simulation Using Silvaco ATLAS Tool

Cited by 7 publications

References 38 publications

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Optimization CIGS/CIGS Tandem Solar Cells by Adjusting Layer Thickness Using Silvaco-Tcad

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

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