Device simulations with A U-Net model predicting physical quantities in two-dimensional landscapes

Abstract

Although Technology Computer-Aided Design (TCAD) simulation has paved a successful and efficient way to significantly reduce the cost of experiments under the device design, it still encounters many challenges as the semiconductor industry goes through rapid development in recent years, i.e. Complex 3D device structures, power devices. Recently, although machine learning has been proposed to enable the simulation acceleration and inverse‑design of devices, which can quickly and accurately predict device performance, up to now physical quantities (such as electric field, potential energy, quantum-mechanically confined carrier distributions, and so on) being essential for understanding device physics can still only be obtained by traditional time-consuming self-consistent calculation. In this work, we employ a modified U-Net and train the models to predict the physical quantities of a MOSFET in two-dimensional landscapes for the first time. Errors in predictions by the two models have been analyzed, which shows the importance of a sufficient amount of data to prediction accuracy. The computation time for one landscape prediction with high accuracy by our well-trained U-Net model is much faster than the traditional approach. This work paves the way for interpretable predictions of device simulations based on convolutional neural networks.

Using U-Net convolutional neural network to model pixel-based electrostatic potential distributions in GaN power MIS-HEMTs

“…Still, the applications of CNN-based approach are limited in the semiconductor research. Recently, one study reported that the pixels of the two-dimensional landscape of low-voltage Si devices could be modeled by a CNN with a U-Net architecture 26 . Note that the advantage of using a U-Net CNN is that, in general, U-Net CNN requires only few images to have a relatively good results 23 – 27 .…”

“…Conversely, the expansive pathway unites feature and spatial information by employing up-convolutions and merging them with high-resolution features obtained from the contracting path through concatenation. However, this work 26 is limited to the dimensional variation with only considering the impact of on-state voltage that directly applied at the surface of the semiconductor with simplified symmetric device design that is not practical for the real device fabrication, which results from the relative compact and shallow network constructed by only 4 layers of contracting path and the expanding path. Furthermore, the impacts of the external dimensional variations, e.g., field plate variations on top of the semiconductor, on the potential distribution inside the semiconductor are not discussed 26 , which is more practical for the consideration of the semiconductor design.…”