Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor

Abstract

This paper presents embedded DRAM device technology utilizing stacked MIM(Metal-Insulator-Metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named "Full Metal DRAM" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO2 is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement.

Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers

“…The RC delay of an inverter chain with F=O ¼ 1 was simulated by using the estimated ÁC under a fixed interconnect length of 50 grids, which corresponds to the typical length in logic IPs used in a 28-nm-node processor. [1][2][3][4] Here, transistors of slow-slow (SS) corners were used under V dd ¼ 0:9 V at À40 C.…”

“…Embedded dynamic random access memories (eDRAMs), which contain standard complementary metal oxide semiconductor (CMOS) logic intellectual property (IP) and DRAM macros, are attractive for realizing high bandwidth, low latency, and low power of the memory-logic interface with small cell size. [1][2][3][4][5] In particular, metal-insulator-metal (MIM) capacitors, such as a TiN top-electrode/ZrO 2 dielectrics/TiN bottom-electrode, have advantages in highspeed DRAM operation owing to the low resistance of the metal electrodes. In a conventional ''capacitor over bit-line (COB)'' structure in eDRAMs, however, cylinder capacitors for storage nodes are located below metal-1 layer (M1).…”

COLK cell : A new embedded DRAM architecture for advanced CMOS nodes

“…Today three architectures are typically used in eDRAM world. Two of them are using stacked capacitor with either CUB cell [1] or COB cell [2] while the third one uses trench capacitor [3]. Major advantages and drawbacks including cost aspect of these 3 types of cells are summarized in Table 1 Schematic cross-section of the COLK cell is presented on Fig.…”