DFM-aware fault model and ATPG for intra-cell and inter-cell defects

Sinha, Arnab; Pandey, Sujay; Singhal, Ayush; Sanyal, Alodeep; Schmaltz, Alan

doi:10.1109/test.2017.8242059

Cited by 20 publications

(5 citation statements)

References 19 publications

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“…Several studies have shown that CAT offers superior test quality and reduces test cost in comparison with n-detect [18,25,28], embedded multi-detect [12,38], or gate-exhaustive test [5,17]. Industrial application has provided experimental evidence of the effectiveness of CAT to reduce test escapes [13,18,19,33,37]. CAT also improves the diagnosis accuracy and efficiency by recording the layout location of potential defects [26,36].…”

Section: Related Prior Workmentioning

confidence: 99%

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Gao

Malagi

et al. 2021

J Electron Test

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Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a defect detection matrix (DDM). In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage 1, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence’s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects.

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Section: Related Prior Workmentioning

confidence: 99%

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Gao

Malagi

et al. 2021

J Electron Test

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“…New technologies give rise to new types of defects [1]- [7] that can be modeled as defect-aware [8]- [9], cell-aware [10]- [14] or gate-exhaustive [15]- [19] faults. These types of faults are described by input patterns of subcircuits or cells.…”

Section: Introductionmentioning

confidence: 99%

Increasing the Fault Coverage of a Truncated Test Set

Pomeranz

2022

ACM Trans. Des. Autom. Electron. Syst.

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Defect-aware, cell-aware and gate-exhaustive faults are described by input patterns of subcircuits or cells that are expected to activate defects. Even with single-cycle faults, an n -input subcircuit can have up to 2 n faults with unique fault detection conditions, resulting in a large test set. Such a test set may have to be truncated to fit in the tester memory or satisfy constraints on test application time. In this case, a loss of fault coverage is inevitable. This article considers the test set denoted by T 1 obtained after truncating a larger test set denoted by T 0 . Suppose that the truncation reduces the set of detected faults from the set denoted by D 0 to the set denoted by D 1 . The procedure described in this article modifies the tests in T 1 to gain the detection of faults from D 0 ∖ D 1 , even at the cost of losing the detection of faults from D 1 . The goal is to reduce the fault coverage loss by computing a test set denoted by T 2 that detects a set of faults denoted by D 2 such that | T 2 | = | T 1 | and | D 2 | > | D 1 |. Experimental results for benchmark circuits demonstrate the ability of the procedure to increase the coverage of gate-exhaustive faults over several iterations.

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“…When DFM guidelines are not adhered to, potential systematic defects may occur. The relationship between DFM guideline violations and potential systematic defects was discussed in References [13,14,34]. In Reference [13], DFM guidelines related to vias on interconnects, and contacts on p-diffusion, are considered.…”

Section: Introductionmentioning

confidence: 99%

“…A more comprehensive set of DFM guidelines is considered in Reference [14]. DFM guidelines related to internal nets of standard cells are considered in Reference [34]. In all these works, the layout sites where DFM guidelines are violated are found, and the affected transistors are identified at the schematic level.…”

Section: Introductionmentioning

confidence: 99%

“…Experimental results and analysis are presented in Section 4. We translate DFM guideline violations into potential short and open defects that are external to cells, and then translate the potential defects into corresponding logic faults using the approach described in References [13,14,34]. We denote the set of faults by F. A test generation procedure is applied to generate a test set T that detects all the detectable faults in F. We denote by U = { f 1 , f 2 , .…”

Section: Introductionmentioning

confidence: 99%

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Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Wang

Pomeranz

Reddy

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

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Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier.In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

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DFM-aware fault model and ATPG for intra-cell and inter-cell defects

Cited by 20 publications

References 19 publications

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Increasing the Fault Coverage of a Truncated Test Set

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

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