DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

Abstract

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk Abstract-This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuckopen faults, we propose a design-for-testability (DFT) logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers trade-off flexibility between test-applicationtime and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase test quality when considering systematic variations. Through SPICE simulations, we show complete recovery of the test quality lost due to PDNs. The proposed method is robust sustaining 80.3% to 98.6% of the achieved test quality under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Reliable Power Gating With NBTI Aging Benefits

“…Logic gates are sized in order to be symmetric for the worst case delay. The V V dd network is modeled with a lumped RC circuit, whose parameters have been derived from [26]: R V V dd = 1Ω, C V V dd = 5f F for the b02 benchmark, C V V dd = 7f F for the NOT chain. Note that the NOT chain (composed by 10 FO4 inverters) is larger than the b02 benchmark and this area difference is reflected by the different values of the parasitic capacitance associated to the V V dd power network in the two case studies.…”

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs

“…The proposed method does not stress the chip during the collection of the signature and the temperature variability is expected to be low. However, if temperature sensors are available during the signature collection and systematic temperature-induced variability is observed, then a similar approach as in [3] can be adopted for higher accuracy.…”

“…Power-gating, which is implemented using either header power switches (pMOS sleep transistors) on the supply power rail V dd or footer power switches (nMOS sleep transistors) on the ground power rail V ss of the power-gated block, has been targeted by testing and diagnosis techniques before [3]- [11]. These techniques target the stuck-open transistor fault model on the power switches that are utilized for disconnecting the virtual supply rail V V dd or the virtual ground rail V V ss , respectively, during stand-by.…”

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure

“…3, is a very small circuit that resides in the power-gating controller and operates as a timeto-digital converter. This type of sensors is already used by power gating DFT infrastructure [30]. The power gating FSM controls the sensor by asserting the measure signal together with the sleep signal in order to collect the d V measurement on every standby operation.…”

“…The discharge time sensor (Section III-A) consists of only a logic AND gate, an inverter, and a clock cycles counter. This type of delay sensor may already be part of the power gating DFT infrastructure [30], [36]. The maximum number of bits |CC| for the counter was |CC| = log 2 (d V (t = 10, T A = 120, T M = 60)/T clk ) = 14 bits, and is obtained with an operating clock period T clk = 1 ns and the maximum d V value that is observed (after time t = 10 years, with average temperature T A = 120°C and temperature during stand-by T M = 60°C) (lower temperature considered) and operating clock period T clk = 1 ns.…”