DFT strategy for Intel microprocessors

Needham, W.; Gollakota, N.

doi:10.1109/test.1996.557029

Cited by 17 publications

(7 citation statements)

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“…Designers always select an appropriate scan manner according to the scale and performance requirement of the design. For instance, full scan is utilized in the test of UltraSparc microprocessor without adverse effect on timing, extra area overhead is 3.50o [3,4]; AMDK7 utilized full scan in the test with 90494 registers support scan test(89.80 o) and 10250 do not (10.2%) [5]; Partial scan is utilized in the spectrum of Intel X86 microprocessors, all the related works are done by hand, which makes the test cost huge [6].…”

Section: Design Of Full Scan Testmentioning

confidence: 99%

Testing of a 32-bit High Performance Embedded Microprocessor

Jing

Zhang

2007

2007 International Symposium on Industrial Embedded Systems

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This paper describes the testable design and fault coverage analysis for a 32-bit high performance embedded microprocessor which is compatible with PowerPC750 ISA. In the test structure, the TAP controller do on-chip standard boundary scan test, full scan test for core logic and MBIST test for embedded memories. In full scan test, all scan registers are organized to 32 scan chains, the area overhead is less than 3%, the critical path is less than 4ns and meets timing requirement. The fault coverage analysis and chip test result demonstrate that the test strategy and test structure are effective for our embedded processor.

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Section: Design Of Full Scan Testmentioning

confidence: 99%

Testing of a 32-bit High Performance Embedded Microprocessor

Jing

Zhang

2007

2007 International Symposium on Industrial Embedded Systems

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“…Observation points are often used in conjunction with built-in test generation in order to increase the fault coverage [Abramovici et al 1995;Basturkmen et al 2002;Lai et al 2004]. They are also used for increasing the fault coverage achieved by functional tests [Needham and Gollakota 1995;Carbine and Feltham 1997;Josephson et al 2001]. The insertion of observation points to increase the transition fault coverage achieved by functional broadside tests, which are generated offline, was described in Pomeranz and Reddy [2008].…”

Section: Introductionmentioning

confidence: 99%

Built-in generation of multicycle functional broadside tests with observation points

Pomeranz

2013

ACM Trans. Des. Autom. Electron. Syst.

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Functional broadside tests allow overtesting to be avoided as part of a scheme that considers both test generation and the analysis of output responses, by ensuring that delay faults are detected under functional operation conditions. Compared with two-cycle tests, multicycle tests allow more faults to be detected with each test, thus reducing the number of tests that need to be applied. They also provide an opportunity for nonfunctional electrical effects, which are caused by switching between modes of operation, to subside before the clock cycles where delay faults are detected. Built-in test generation facilitates at-speed testing and reduces the test data volume. Motivated by these observations, this article describes the modification of a built-in test generation method for two-cycle functional broadside tests so as to generate multicycle functional broadside tests. The size of the hardware is not increased by the modification. The article investigates the following issues related to this method: (1) the effect of using multicycle tests on the number of tests that need to be applied; (2) fault simulation for tailoring the test generation hardware to a circuit that takes into account, to different extents, the need to allow nonfunctional electrical effects to subside; (3) the insertion of observation points in order to increase the transition fault coverage.

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“…An overview of these with their advantages and limitations is provided in [2]. Another standard technique for test and debug is the use of scanout chains [4,5] to sample state of internal signals. Scanout chains are basically scan chains which are used to monitor internal signals.…”

Section: Dft and Dfd Strategiesmentioning

confidence: 99%

“…The paths that need to be tested using the Delay Scan Chain are critical paths above a certain designer specified threshold, internal signals of particular logic blocks and signals that are difficult to observe [4]. As mentioned before, two vectors are required to test a path for delay faults and can be applied using enhanced scan, skewed-load or broadside schemes [7].…”

Section: Delay Test and Debug Schemementioning

confidence: 99%

Delay fault testing and silicon debug using scan chains

Datta

Sebastine

Abraham

Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.

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This paper describes a novel technique to reuse the existing scanpaths in a chip for delay fault testing and silicon debug. Efficient test and debug techniques for VLSI chips are indispensable in Deep Submicron technologies. A systematic debug scheme is also necessary in order to reduce time-to-market. Due to stringent timing requirements of modern chips, test and debug schemes have to be tailored for detection and debug of functional defects as well as delay faults quickly and efficiently. The proposed technique facilitates an efficient scheme for detecting and debugging delay faults and has minimal area and power overhead.

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DFT strategy for Intel microprocessors

Cited by 17 publications

References 0 publications

Testing of a 32-bit High Performance Embedded Microprocessor

Testing of a 32-bit High Performance Embedded Microprocessor

Built-in generation of multicycle functional broadside tests with observation points

Delay fault testing and silicon debug using scan chains

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