DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

Satagopan, Venkat; Bhaskaran, Bonita; Al-Assadi, Waleed K.; Smith, Scott C.; Kakarla, S.

doi:10.1109/tvlsi.2007.903945

Cited by 15 publications

(16 citation statements)

References 10 publications

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“…There are mainly two approaches in the literature to make the NCL circuits testable: limited insertion of control/observation points to increase fault coverage [10], [11], and synchronous modeling of NCL pipelines to make them compatible with synchronous ATPG tools and using scan chain technique [12].…”

Section: Related Work 31ncl Specific Dft Methodologiesmentioning

confidence: 99%

“…The XOR tree, however, requires a lot of space, especially for more complex designs with several pipeline stages, and also increases the number of primary outputs significantly, so this is not very practical. In order to cope with low fault coverage, Satagopan et al [10] then proposed to break the internal feedback path inside every NCL gate and insert a latch. This technique is shown to significantly improve testability (almost 100% fault coverage), but it requires substantial area overhead, which makes it impractical.…”

Section: 11limited Insertion Of Control/observation Pointsmentioning

confidence: 99%

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Design for Testability Implementation Of Dual Rail Half Adder Based on Level Sensitive Scan Cell Design

2017

IJRTER

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Abstract-Design for testability (DFT) refers to hardware design styles or it is an added hardware that reduces test generation complexity and test cost, also increases test quality. Sleep Convention Logic (SCL) is an asynchronous logic style which is based on Null Convention Logic (NCL). In the SCL the combinational blocks are made of threshold gates. SCL utilizes power gating method to further reduce the power consumption by incorporating the sleep signal in every single gate. There are currently no DFT methodologies existing for SCL. But in the current NCL, specific DFT methods cannot be directly used due to the sleep mechanism for power gating. The aim of this paper is to analyze various stuck-at-faults within SCL pipelines. Hence by using scan based testing methodology the SCL circuit is analyzed at the cost of usual area overhead .The proposed methodology is based on fault analysis.Keywords-sleep convention logic, null convention logic, dual rail, power gating technique, Design for testability.I. INTRODUCTION Design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The tests are generally driven by test programs that execute using automatic test equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. The diagnostic information can be used to locate the source of the failure. The automatic test equipment is an instrument used to apply test patterns to device-under-test (DUT), analyze the responses from the DUT, and mark the DUT as good or bad. The DUTis also called as the circuitunder-test (CUT).Sleep convention logic (SCL) is a self-timed asynchronous pipeline style that offers inherent power-gating, resulting in ultra-low power consumption while idle. SCL combines the ideas of NCL with early completion and MTCMOS power-gating. Sleep convention logic (SCL), is also known as a variant of NULL convention logic (NCL) [1], [2] that takes the advantage of the MTCMOS power-gating technique [3], [4] to further reduce the power consumption. Most of these advantages are the direct result of applying the sleep mechanism to the circuit. The first obvious advantage is reducing the static power consumption due to power-gating through high-Vth transistors.The application of MTCMOS to the NCL circuits comes with interesting architectural changes that ultimately results in area and performance advantages as well. The aim of this paper is to analyze the various stuck-at faults within an SCL pipeline and propose a comprehensive scan-based testing methodology that provides for high test coverage by introducing the scan chain. Level Sensitive Scan Design (LSSD) is the DFT method used to test the sleep convention logic. The proposed DFT methodology is based on scan chain design, which is very popular in industry, and it provides for high test coverage.

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Section: Related Work 31ncl Specific Dft Methodologiesmentioning

confidence: 99%

Section: 11limited Insertion Of Control/observation Pointsmentioning

confidence: 99%

Design for Testability Implementation Of Dual Rail Half Adder Based on Level Sensitive Scan Cell Design

2017

IJRTER

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“…Banerjee et al in [13] The schemes proposed in [9] focused on breaking the feedback paths, both globally and locally. Breaking such loops ensures that the complexity of the test is reduced to that of a combinational circuit.…”

Section: Previous Workmentioning

confidence: 99%

“…Wires connecting components do not need to adhere to the isochronic fork assumption. NCL circuits often outperform other delay-insensitive methods because they target a wider range of logical operators, as opposed to others that target standard, more restricted sets [1], [4], [5] Testing asynchronous circuits has been a major challenge [7]- [9]. In order to compete with their synchronous counterparts, asynchronous schemes must be capable of producing VLSI circuits that are at least as readily testable as synchronous circuits.…”

Section: Introductionmentioning

confidence: 99%

“…In order to compete with their synchronous counterparts, asynchronous schemes must be capable of producing VLSI circuits that are at least as readily testable as synchronous circuits. Asynchronous NCL designs present a complex test case to the tester and to DFT tools [9]- [12]. Testability can be strengthened by making design modifications that are dormant under normal circuit operation and effective only during test mode [8].…”

Section: Introductionmentioning

confidence: 99%

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Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Al-Assadi

Kakarla

2008

2008 IEEE International Test Conference

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Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using SCOAP (Sandia Controllability and Observability Program) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits. *

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Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Al-Assadi

Kakarla

2008

J Electron Test

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DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

Cited by 15 publications

References 10 publications

Design for Testability Implementation Of Dual Rail Half Adder Based on Level Sensitive Scan Cell Design

Design for Testability Implementation Of Dual Rail Half Adder Based on Level Sensitive Scan Cell Design

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

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