No abstract

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using SCOAP (Sandia Controllability and Observability Program) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits. *

As Integrated Circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is an important phenomenon that must be taken into account. Also, crosstalk noise has emerged as a serious problem in recent years, because more and more devices and wires have been packed on electronic chips. Despite being more immune to crosstalk noise than their ASIC (Application Specific Integrated Circuit) counterparts, the dense interconnected structures of FPGAs (Field Programmable Gate Arrays) invite more vulnerabilities to crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults caused by crosstalk noise. This paper proposes a new approach for detecting effects such as glitches and delays in transition due to crosstalk noise in FPGAs. This approach is similar to the BIST (Built-in Self Test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any extra overhead for testing.

No abstract

No abstract