Diagnosis and correction of logic design errors in digital circuits

Chung, Pi-Yu; Wang, Yimin; Hajj, I.N.

doi:10.1145/157485.165003

Cited by 65 publications

(35 citation statements)

References 11 publications

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“…The number of transformation locations returned by the diagnosis are reported in Column 2. The formal method in [17] is utilized to answer with certainty whether there exists a modification that corrects the design at those locations. In detail, that method does not return the actual transformation but indicates whether some amount of transformation may or may not correct the design at the particular location.…”

Section: Methodsmentioning

confidence: 99%

Sequential logic rectifications with approximate SPFDs

Sinha¹,

Veneris²,

Smith³

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFD-based sequential logic transformation methodology to tackle the problem with no sacrifice on performance. It first presents an efficient approach to construct approximate SPFDs (aSPFDs) for sequential circuits. Then, it demonstrates an algorithm using aSPFDs to perform the desirable sequential logic transformations using both combinational and sequential don't cares. Experimental results show the effectiveness and robustness of the approach.

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Section: Methodsmentioning

confidence: 99%

Sequential logic rectifications with approximate SPFDs

Sinha¹,

Veneris²,

Smith³

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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show abstract

“…Debugging techniques relying on simulation [7]- [10] and BDDs [7], [11] were among the earliest. These solutions perform well under certain conditions but the size of modern designs poses a challenge in their ability to scale.…”

Section: A Simulation and Bdd-based Techniquesmentioning

confidence: 99%

“…Although this process is memory efficient, its run-time and resolution degrades with sequential designs and multiple errors limiting its applicability. BDD-based methods [11] demonstrate an algebraic solution to debugging single and multiple errors. Although effective for single errors, BDDs are limited by memory issues as the design scales.…”

Section: A Simulation and Bdd-based Techniquesmentioning

confidence: 99%

From RTL to silicon: The case for automated debug

Veneris

Keng

Safarpour

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Abstract-Computer-aided design tools are continuously improving their scalability and efficiency to mitigate the high cost associated with designing and fabricating modern VLSI systems. A key step in the design process is the root-cause analysis of detected errors. Debugging may take months to close, introduce high cost and uncertainty ultimately jeopardizing the chip release date. This study makes the case for debug automation in each part of the design flow (RTL to silicon) to bridge the gap. Contemporary research, challenges and future directions motivate for the urgent need in automation to relieve the pain from this highly manual task.

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“…During the chip design cycle, small structural transformations in logic netlists are often required to accommodate different goals, For example, the designer needs to rectify designs that fail functional verification at locations identified by a debugging program [1], [2]. In the case of engineering changes (EC) [3], a logic netlist is modified to reflect specification changes at a higher level of abstraction.…”

Section: Introductionmentioning

confidence: 99%

Automating Logic Transformations With Approximate SPFDs

Yang

Sinha

Veneris

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-During the VLSI design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It first presents a simulation-based formulation to approximate SPFDs and avoid the memory/time explosion issue inherent with the original representation. Then it uses this new data structure to devise the required transformations dynamically without the need of a static dictionary model. The methodology is applied to both combinational and sequential designs with transformations at a single or multiple locations. An extensive suite of experiments documents the benefits of the proposed methodology when compared to existing practices.

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Diagnosis and correction of logic design errors in digital circuits

Cited by 65 publications

References 11 publications

Sequential logic rectifications with approximate SPFDs

Sequential logic rectifications with approximate SPFDs

From RTL to silicon: The case for automated debug

Automating Logic Transformations With Approximate SPFDs

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