Diagnosis and Layout Aware (DLA) scan chain stitching

Ye, Jing; Huang, Yu; Hu, Yu; Cheng, Wu-Tung; Guo, Ruifeng; Lai, Liyang; Tai, Ting-Pu; Li, Xiaowei; Changchien, Weipin; Lee, Daw-Ming; Chen, Ji-Jan; Eruvathi, Sandeep C.; Kumara, Kartik K.; Liu, Charles; Pan, S.C.

doi:10.1109/test.2013.6651929

Cited by 4 publications

(4 citation statements)

References 45 publications

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“…We compare our method with the method proposed in "Comparison with Diagnosis and Layout Aware (DLA) Scan Chain Stitching" [31] and ours. The result is illustrated in Table X.…”

Section: Comparison Of Maximum Range Of Suspect Faulty Scan Cellsmentioning

confidence: 99%

“…Recently, Ye et al [31] proposed an intelligent method using simulated annealing for scan chain partitioning and ant colony optimization for scan chain reordering to improve the resolution of scan chain diagnosis. Nevertheless, [31] lacks a precise cost function to evaluate the effect of swapping for scan chain diagnosis.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, [31] lacks a precise cost function to evaluate the effect of swapping for scan chain diagnosis. Moreover, the run time of their simulated annealing and ant colony optimization method is very long for large-sized circuits.…”

Section: Introductionmentioning

confidence: 99%

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Utilizing Circuit Structure for Scan Chain Diagnosis

Hsieh

Lan

et al. 2014

IEEE Trans. VLSI Syst.

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Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip-flops. After the partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC'99 benchmarks.Index Terms-Design for testability, digital circuits, fault diagnosis.

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“…We compare our method with the method proposed in "Comparison with Diagnosis and Layout Aware (DLA) Scan Chain Stitching" [31] and ours. The result is illustrated in Table X.…”

Section: Comparison Of Maximum Range Of Suspect Faulty Scan Cellsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Utilizing Circuit Structure for Scan Chain Diagnosis

Hsieh

Lan

et al. 2014

IEEE Trans. VLSI Syst.

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“…Furthermore, fault locations can be diagnosed by analyzing scan test results, leading to an immediate improvement in the yield by improving the processes for those sites. However, a scan architecture that penetrates all flip-flops in a circuit is distributed throughout the circuit [1], so as many as 50% of the chip failures occur because of the faults in the scan architecture [2]. Many of the defects in the initial process can be analyzed through fault analysis in the scan chain, but further analysis of defects across all logic is possible only if the faults appearing in the scan chain are removed.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Scan Architecture for High Diagnostic Resolution

2021

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Scan chain diagnosis is essential to solving yield-reduction problem caused by the miniaturization of manufacturing process. The accurate diagnosis of scan chain faults that frequently occur in the initial process is vital for rapidly improving yield. Moreover, the importance of scan chain diagnosis with a high resolution for the multiple faults is increasing because multiple faults occur in the early stages of the process, further increasing the cost of physical failure analysis. Although multiple faults can be diagnosed with existing methods, a high diagnostic resolution is difficult to achieve in the early stages of the process (where many faults occur) due to the rapid increase in the number of diagnosed fault candidates as the number of actual faults in the circuit increases. In this paper, a novel reconfigurable scan architecture that reconfigures the diagnosis paths and a test algorithm that uses this scan architecture are proposed to reduce the number of diagnosed fault candidates in the scan chain diagnosis with multiple circuit faults. Experimental results indicate that the proposed method achieves the higher diagnostic resolution for multiple faults than conventional methods. In addition, the proposed method reduces the routing overhead by scan partitioning.

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