Diagnosis of Local Spot Defects in Analog Circuits

Abstract

International audienceWe present a method for diagnosing local spot defects in analog circuits. The method aims to identify a subset of defects that are likely to have occurred and suggests to give them priority in a classical failure analysis. For this purpose, the method relies on a combination of multiclass classifiers that are trained using data from fault simulation. The method is demonstrated on an industrial large-scale case study. The device under consideration is a controller area network transceiver used in automobile systems. This device demands high-quality control due to the reliability requirements of the application wherein it is deployed. The diagnosis problem is discussed by taking into consideration the realities of this case study

Multiple soft fault diagnosis of DC analog CMOS circuits designed in nanometer technology

“…The measurement accuracy and the constants of the computation Fig. 7 A rail-to-rail input buffer The results of various multiple soft fault diagnoses are summarized in Tables 6,7,8,9. They comprise three sets of the simultaneous variations of all the channel lengths in NMOS transistors (Table 6), in PMOS transistors (Table 7), and three sets of the simultaneous variations of all the oxide thicknesses in NMOS transistors (Table 8) and the PMOS transistors (Table 9).…”

“…If a fault is open circuit or short circuit, it is called hard or catastrophic. In integrated circuits physical imperfections, such as near-opens or near-shorts may occur as spot defects [7,10,21,22]. The methods dedicated to soft fault diagnosis usually exploit the simulation after test approach, where circuit simulations take place after any testing.…”

Diagnosis of Soft Spot Short Defects in Analog Circuits Considering the Thermal Behaviour of the Chip

“…If a faulty parameter drifts from its tolerance range, but does not lead to some topological changes, the fault is said to be the soft or parametric one. Most physical failures (80-90)% in integrated circuits are opens and shorts [9][10]21]. In both CMOS and BJT circuits (70-80)% of failures are shorts and (10-20)% opens.…”

Optimal Method for Catastrophic Faults Diagnosis in RC Ladder Network

“…Though this algorithm can be used for medium and large networks also, it is very costly. Huang et al [7] have given a method to diagnose the local spot defects in analog circuit. This method is based on the combination of multiclass classifiers that are trained using data from fault simulation.…”