Diagnostic Test Generation for Arbitrary Faults

Bhatti, Naresh K.; Blanton, R. D.

doi:10.1109/test.2006.297647

Cited by 26 publications

(18 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is still more efficient compared to [7] because only two, and not four, copies of CUT are required. SAT based diagnostic test generation procedures have been proposed [3] for the transition fault model. A SAT formulation may be too complex for large designs.…”

Section: Background and Motivationmentioning

confidence: 99%

Reduced complexity test generation algorithms for transition fault diagnosis

Agrawal

2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

Abstract-To distinguish between a pair of transition faults, we need to find a test vector pair (LOC or LOS type) that produces different output responses for the two faults. By adding a few logic gates and one modeling flip-flop to the circuit under test (CUT), we create a diagnostic ATPG model usable by a conventional single stuck-at fault test pattern generator. Given a transition fault pair, this ATPG model either finds a distinguishing test or proves the faults to be equivalent. An efficient diagnostic fault simulator is devised to find undistinguishable fault pairs from a fault list by a test vector set. The number of fault pairs that needs to be targeted by the ATPG is greatly reduced after diagnostic fault simulation. We use a previously proposed diagnostic coverage (DC) metric to determine the distinguishability (diagnosability) of a test vector set. Experimental results show improved DC for benchmark circuits after applying the proposed diagnostic ATPG algorithms.

show abstract

Section: Background and Motivationmentioning

confidence: 99%

Reduced complexity test generation algorithms for transition fault diagnosis

Agrawal

2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

show abstract

“…In [9], diagnostic test generation methods for delay faults have been proposed. In [10], a diagnostic test generation method for various types of faults, including brides, transitions and stuck-opens, has been proposed, where the problem is solved by SAT formulation.…”

Section: Introductionmentioning

confidence: 99%

“…The paper [10] has also generated diagnostic test vectors and identified indistinguishable faults for transition faults by a SAT-based approach. It is not easy to compare the performance between the method [10] and our method currently.…”

Section: Introductionmentioning

confidence: 99%

“…It is not easy to compare the performance between the method [10] and our method currently. However, in the experiments of the paper [10], only ISCAS'85 combinational circuits were dealt with among benchmark circuits, and LOC test was not considered. There are some circuits that are difficult to deal with by the SATbased approach.…”

Section: Introductionmentioning

confidence: 99%

“…There are some circuits that are difficult to deal with by the SATbased approach. In the paper [10], it was mentioned that dealing with c6288 was difficult, and experimental results on c6288 were not given. (ATPG tools can relatively easily deal with c6288.)…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool

Higami

Ohno

Yamaoka

et al. 2012

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYIn this paper, we propose a test generation method for diagnosing transition faults. The proposed method assumes launch on capture test, and it generates test vectors for given fault pairs using a stuck-at ATPG tool so that they can be distinguished. If a given fault pair is indistinguishable, it is identified, and thus the proposed method achieves a complete diagnostic test generation. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic gates are inserted in a CUT during the test generation process. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify indistinguishable fault pairs.

show abstract

Generalized Fault Modeling for Logic Diagnosis

Wunderlich

Holst

2009

Models in Hardware Testing

View full text Add to dashboard Cite

Diagnostic Test Generation for Arbitrary Faults

Cited by 26 publications

References 28 publications

Reduced complexity test generation algorithms for transition fault diagnosis

Reduced complexity test generation algorithms for transition fault diagnosis

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool

Generalized Fault Modeling for Logic Diagnosis

Contact Info

Product

Resources

About