Generalized Fault Modeling for Logic Diagnosis

Wunderlich, Hans-Joachim; Holst, Stefan

doi:10.1007/978-90-481-3282-9_5

Cited by 15 publications

(10 citation statements)

References 35 publications

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“…Separate instances of the Hope fault simulator are dynamically created for the considered gate-level models. While the algorithmic optimizations in Hope target the stuck-at fault model, they can be extended to other structural fault models using the concept of conditional stuck-at faults [34]. Figure 3 shows the interaction between the core wrapper, the Hope fault simulator instance and the faulty machine at transaction-level.…”

Section: Methodsmentioning

confidence: 99%

Efficient multi-level fault simulation of HW/SW systems for structural faults

Baranowski

Carlo

Hatami

et al. 2011

Sci. China Inf. Sci.

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In recent technology nodes, reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design. While traditional fault simulation techniques based on low-level models at gate-and register transfer-level offer high accuracy, they are too inefficient to properly cope with the complexity of modern embedded systems. Moreover, they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available, which is highly required to increase the efficiency and quality of the design flow. Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system. This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate-and transaction-level models in an integrated simulation environment. It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low. Moreover, since only selected portions of the system require low-level models, early exploration of different design alternatives is efficiently supported. Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average. CitationBaranowski R, Di Carlo S, Hatami N, et al. Efficient multi-level fault simulation of HW/SW systems for structural faults.

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Section: Methodsmentioning

confidence: 99%

Efficient multi-level fault simulation of HW/SW systems for structural faults

Baranowski

Carlo

Hatami

et al. 2011

Sci. China Inf. Sci.

Self Cite

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show abstract

“…Separate instances of the Hope fault simulator are dynamically created for the considered gate-level models. While the algorithmic optimizations in Hope target the stuck-at fault model, they can be extended to other structural fault models using the concept of conditional stuck-at faults [33]. Figure 3 shows the interaction between the core wrapper, the Hope fault simulator instance and the faulty machine at transaction-level.…”

Section: Methodsmentioning

confidence: 99%

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

Kochte

Zoellin

Baranowski

et al. 2010

2010 19th IEEE Asian Test Symposium

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In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at gate-and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-theart techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approach.

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“…We examine the diagnostic resolution for arbitrary defect using the Conditional Line Flip (CLF) calculus from [13]. A CLF consists of a victim signal and an arbitrary activation condition.…”

Section: Conditional Line Flip Calculusmentioning

confidence: 99%

Embedded Test for Highly Accurate Defect Localization

Mumtaz

Imhof

Holst

et al. 2011

2011 Asian Test Symposium

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Modern diagnosis algorithms are able to identify the defective circuit structure directly from existing fail data without being limited to any specialized fault models. Such algorithms however require test patterns with a high defect coverage, posing a major challenge particularly for embedded testing. In mixed-mode embedded test, a large amount of pseudorandom (PR) patterns are applied prior to deterministic test pattern. Partial Pseudo-Exhaustive Testing (P-PET) replaces these pseudo-random patterns during embedded testing by partial pseudo-exhaustive patterns to test a large portion of a circuit fault-model independently. The overall defect coverage is optimized compared to random testing or deterministic tests using the stuck-at fault model while maintaining a comparable hardware overhead and the same test application time. This work for the first time combines P-PET with a fault model independent diagnosis algorithm and shows that arbitrary defects can be diagnosed on average much more precisely than with standard embedded testing. The results are compared to random pattern testing and deterministic testing targeting stuck-at faults.

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Generalized Fault Modeling for Logic Diagnosis

Cited by 15 publications

References 35 publications

Efficient multi-level fault simulation of HW/SW systems for structural faults

Efficient multi-level fault simulation of HW/SW systems for structural faults

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

Embedded Test for Highly Accurate Defect Localization

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