Diagnostic test pattern generation for sequential circuits

Hartanto, I.; Boppana, Vamsi; Patel, J.H.; Fuchs, W.K.

doi:10.1109/vtest.1997.600264

Cited by 32 publications

(23 citation statements)

References 27 publications

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“…That work derived results on avoiding the explicit proving of specific indistinguishability relations. Results on diagnostic test pattern generation for large sequential circuits have also been reported in recent work [14]. However, in contrast with this present paper, there was no attempt in the previous work to re-use the results already obtained during DATPG.…”

Section: Introductionsupporting

confidence: 61%

“…Undetected faults (using HITEC [21] vectors) are then removed from this list of faults to obtain the set of faults, indicated by NuFscNfsr. These faults are processed with the new fault collapsing diagnostic test generator that was built on top of the diagnostic test generator DIAGGEN [14] to obtain the sequentially collapsed list of faults, SeqcNuFscNfsr. The untestable faults that were removed were then added back to this list of faults to get the list of faults indicated by SeqcFscNfsr.…”

Section: Results On Fault Collapsingmentioning

confidence: 99%

See 1 more Smart Citation

Dynamic Fault Collapsing and Diagnostic Test Pattern Generation for Sequential Circuits

Boppana¹,

Fuchs²

1998

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In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by developing results that permit dynamic, fully functional, collapsing of candidate faults. Fault collapsing permits the organization of faults into disjoint partitions based on the indistinguishability relation. These results are used to develop a diagnostic test pattern generation algorithm that has the same order of complexity as that of detection-oriented test generation (ATPG). Techniques to identify untestable faults, based on exploiting indistinguishability identification, are also presented. Experimental results are presented on the ISCAS 89 benchmark circuits.

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Section: Introductionsupporting

confidence: 61%

Section: Results On Fault Collapsingmentioning

confidence: 99%

Dynamic Fault Collapsing and Diagnostic Test Pattern Generation for Sequential Circuits

Boppana¹,

Fuchs²

1998

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“…Therefore, to improve the diagnosability, special patterns with higher diagnosability are needed in addition to the detection test set [14]- [18]. The goal of diagnostic test generation is to find a test such that the circuit produces different responses for different faults.…”

Section: A Diagnostic Test Generationmentioning

confidence: 99%

“…The goal of diagnostic test generation is to find a test such that the circuit produces different responses for different faults. Diagnostic test-generation methods in [14]- [16] are based on various circuit modification techniques that allow a standard test-generation algorithm for fault detection to be directly used for diagnostic test generation. The diagnostic test-generation procedure proposed in [17] starts with a complete fault-detection test set.…”

Section: A Diagnostic Test Generationmentioning

confidence: 99%

Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation

Lin

Cheng

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we propose two fault-diagnosis methods for improving multiple-fault diagnosis resolution. The first method, based on the principle of single-fault activation and single-output observation, employs a new circuit transformation technique in conjunction with the use of a special type of diagnostic test pattern, named single-observation single-location-at-a-time (SO-SLAT) pattern. Given a list of candidate suspects (which could be stuck-at, transition, bridging, or other faults obtained by any existing diagnosis method), we generate a set of SO-SLAT patterns, each of which attempts to activate only one fault in the list and propagate its effects only to a specific observation point. Observing the responses of the circuit under diagnosis to the SO-SLAT patterns helps more precisely determine whether each fault suspect is a true or false candidate. The method can tolerate most of the timing hazards for a more accurate diagnosis of failures caused by timing faults. The second method generates and applies limited-cycle sequential tests, based on a Boolean satisfiability solver, to identify multiple defective signals which can jointly explain the circuit's faulty behavior. These two methods can be applied independently and/or jointly after any existing state-of-the-art diagnosis process to further improve the diagnosis resolution. The experimental results demonstrate the effectiveness of the proposed methods for diagnosing multiple faults, including timing faults.Index Terms-Boolean satisfiability, diagnosis, testing, very large scale integration (VLSI).

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“…These methods are fast but they have pessimistic results since they operate on fan-out free circuit regions only. Functional fault equivalence methods are more expensive but they typically identify more classes [1,2,7,9,12]. Some of these methods [1,2,12] use logic implications and/or dominator information to prove equivalence.…”

Section: Introductionmentioning

confidence: 99%

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Veneris

Chang

Abadir³

et al. 2005

J Electron Test

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Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS'85 and full-scan ISCAS'89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.

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Diagnostic test pattern generation for sequential circuits

Cited by 32 publications

References 27 publications

Dynamic Fault Collapsing and Diagnostic Test Pattern Generation for Sequential Circuits

Dynamic Fault Collapsing and Diagnostic Test Pattern Generation for Sequential Circuits

Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

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