DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory

Villavieja, Carlos; Karakostas, Vasileios; Vilanova, Lluís; Etsion, Yoav; Ramírez, Alex; Mendelson, Avi; Navarro, Nacho; Cristal, Adrián; Unsal, Osman S.

doi:10.1109/pact.2011.65

Cited by 80 publications

(65 citation statements)

References 20 publications

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“…APIC implementations vary; depending on the APIC technology, KVM converts broadcast IPIs into a loop of individual IPIs, or a loop across processor clusters. We have profiled the overheads of IPIs using microbenchmarks on Haswell systems, and like past work [10,33], find that they are expensive, consuming thousands of clock cycles. If the receiving CPUs are running vCPUs, they suffer VM exits, compromising 3 from Sec.…”

Section: Page Remapping Anatomymentioning

confidence: 95%

“…Past work has shown that translation coherence overheads can easily consume 10-30% of system performance [10,32,33]. These overheads are even more alarming on virtualized systems, which are used in the server and cloud settings expected to be early adopters of heterogeneous memories.…”

Section: Introductionmentioning

confidence: 99%

“…This view is inspired by prior work on UNITD [32], which showcased the potential of hardware translation coherence. Unfortunately, UNITD is energy inefficient and, like other recent proposals [10,33], cannot support virtualized systems. In response, we propose hardware translation invalidation and coherence or HATRIC, a hardware mechanism to tackle these problems and meet 1 -3 .…”

Section: Introductionmentioning

confidence: 99%

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Hardware Translation Coherence for Virtualized Systems

YanZi

VeselýJán

CoxGuilherme

et al. 2017

SIGARCH Comput. Archit. News

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To improve system performance, modern operating systems (OSes) often undertake activities that require modification of virtual-to-physical page translation mappings. For example, the OS may migrate data between physical frames to defragment memory and enable superpages. The OS may migrate pages of data between heterogeneous memory devices. We refer to all such activities as page remappings. Unfortunately, page remappings are expensive. We show that translation coherence is a major culprit and that systems employing virtualization are especially badly affected by their overheads. In response, we propose hardware translation invalidation and coherence or HATRIC, a readily implementable hardware mechanism to piggyback translation coherence atop existing cache coherence protocols. We perform detailed studies using KVM-based virtualization, showing that HATRIC achieves up to 30% performance and 10% energy benefits, for per-CPU area overheads of 2%. We also quantify HATRIC's benefits on systems running Xen and find up to 33% performance improvements.

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Section: Page Remapping Anatomymentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hardware Translation Coherence for Virtualized Systems

YanZi

VeselýJán

CoxGuilherme

et al. 2017

SIGARCH Comput. Archit. News

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“…The impact of adding these TLBs is not significant since they need not be very large (see Table 1). We also use a TLB directory to minimize the overhead of TLB shootdowns [34].…”

Section: Isa Extensionsmentioning

confidence: 99%

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

García

Rico

Villavieja

et al. 2016

Int J Parallel Prog

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Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtimedirected prefetching and more specifically runtime-directed block prefetching.This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to.Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32% and 10% on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18% and 3% on average in energy-to-solution.

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“…Villavieja et al [84] propose DiDi, a directory-like solution for TLB coherence, which introduces a shared second level TLB acting as a dictionary directory (DiDi), tracking every address translation stored in first-level TLBs and their presence bitmap. DiDi ensure up-to-date information by intercepting all insertions and evictions on L1 TLBs.…”

Section: Tlb Coherencementioning

confidence: 99%

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

García¹

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AcknowledgmentCuatro años de esfuerzo dan para mucho. Echándo la vista atrás, muchas son las personas que me han apoyado, muchos los que me han escuchado. Gracias a todos.A Ramón y Lola. Sin ellos, sin su apoyo y su amor, no habría llegado hasta aquí. Sin su inspiración no habría siquiera empezado el camino. Ellos plantaron la semilla de la curiosidad, tan necesaria para superar la frustración y las dificultades a las que todo investigador tiene que enfrentar en su camino.A Víctor. Hermano y amigo. El espejo en el que me miro. Me has dado fuerza en cada etapa de mi vida. Gracias por todo. Habrá que pensar una buena ruta en bici para celebrarlo.A Carla. Por su paciencia, por su ayuda, por respaldarme cuando lo he necesitado. Siempre me has animado a seguir adelante y has permanecido a mi lado en cada etapa del doctorado. Más que eso, eres uno de los pilares principales de mi vida.A Salomé, Eloy y Sergio. Por quererme y aceptarme como uno más de la familia. Realmente yo lo siento del mismo modo. Gracias.A mis amigos. Samuel, Eduardo, Manolo. Ya sea jugando a algún juego, organizándo viajes juntos, o saliendo de fiesta o a tomar algo, siempre habéis estado ahí, siendo partícipes de mis logros y mis frustraciones. Tanto como yo de las vuestras. Y espero que siga siendo así por muchos, muchos años.Allá por 2007 empezaba mi andadura por la universidad, hace ya diez años.Ésta ha sido mi segunda casa, y le debo mucho. Y tengo muchos que agradecer también a toda la gente que he conocido en este etapa. Incluyendoéstaúltima fase en el Grupo de Arquitecturas Paralelas.Por supuesto y ante todo a mis directores, Alberto, Antonio y Maria Engracia. Me habéis guiado e inspirado, desafiado y ayudado en cada etapa de mi doctorado. Vuestra paciencia y esfuerzo han sido claves para la consecución de este trabajo. He aprendido mucho durante estos años. No sólo en materia de arquitectura de computadores, sino también en investigación científica; a amarla, a observar los pequeños detalles, a analizar los datos y entender qué esta ocurriendo para así poder seguir avanzando. Ellos han cambiado mi vida, profesional y personal, para siempre.A Núria, Salva y Eduardo. No nos vemos tanto como antes, nuestras vidas, sus obligaciones, nos alejan. Pero aún nos quedarán esas tardes de cervezas para ponernos al día. Siempre.A mis compañeros de laboratorio. José Vicente, José María, Migue, Vicent, Joan, Fran, Javi, Roberto, Carlos, Santi, y un largo etcétera. A los que se fueron, Knut, Mario, Crispín. Tantos y tantos. A todos os debo algo. Lo que ha unido el BoardGameArena que no lo separen nuestras exitosas carreras en el extranjero, como un tren de mercancías desbocado y sin frenos. Y por supuesto a Ricardo. El verdadero pilar del laboratorio, en lo técnico y en lo personal. Tu increible paciencia y dedicación te hacen pieza central del trabajo de todos nosotros en el grupo.

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DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory

Cited by 80 publications

References 20 publications

Hardware Translation Coherence for Virtualized Systems

Hardware Translation Coherence for Virtualized Systems

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

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