Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

Jurczak, M.; Skotnicki, T.; Gwoziecki, R.; Paoli, M.; Tormen, B.; Ribot, P.; Dutartre, D.; Monfray, S.; Galvier, J.

doi:10.1109/16.936706

Cited by 84 publications

(45 citation statements)

References 13 publications

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“…Incorporation of a deposited oxide region on top of the pillar and the thicker oxide grown on the highly doped poly-Si extrinsic drain contact can reduce significantly the gate-drain capacitance. A study using MOS-capacitors has demonstrated a 5-fold reduction in parasitic overlap capacitance using FILOX and a thick top oxide [3]. To summarise the study, we show in Fig.…”

Section: Reduction Of Parasitic Overlap Capacitancementioning

confidence: 99%

“…1. Reduction of gate-source overlap capacitance (bottom of pillar) is achieved by a LOCOS type process ÔFILOXÕ [3]. Fig.…”

Section: Reduction Of Parasitic Overlap Capacitancementioning

confidence: 99%

“…Notice that the transistor can be considered to operate in either source up, or down modes although not all architectural features are appropriate for bi-directional operation. Specifically we identify the use of a so-called dielectric pocket (DP) to control SCE (source down mode) [2,3], thickened oxide regions, including a novel fillet oxidation (FILOX) overlap process to minimize overlap capacitance [2,4] and the use of polySiGe regions to reduce the emitter efficiency of the PBT (source up mode) [5]. We now consider these concepts, and indicate the expected performance advantage in the ITRS context.…”

Section: Introductionmentioning

confidence: 99%

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Recent developments in deca-nanometer vertical MOSFETs

Hall

Donaghy

Buiu

et al. 2004

Microelectronic Engineering

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We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.

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Section: Reduction Of Parasitic Overlap Capacitancementioning

confidence: 99%

“…1. Reduction of gate-source overlap capacitance (bottom of pillar) is achieved by a LOCOS type process ÔFILOXÕ [3]. Fig.…”

Section: Reduction Of Parasitic Overlap Capacitancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Recent developments in deca-nanometer vertical MOSFETs

Hall

Donaghy

Buiu

et al. 2004

Microelectronic Engineering

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“…the dielectric pocket). After dielectric pocket formation, the selective epitaxy was carried out to fulfill the depression in the S/D regions [3].…”

Section: Fabrication Feasibilitymentioning

confidence: 99%

“…Recently, we proposed a new device architecture called Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET that combines the advantages of Silicon On Nothing (SON) [2] and Insulated Shallow Extension (ISE) MOSFET [3] showing superior device performance as compared to other devices for DC as well as the analog applications even at the higher temperatures [4,5]. The advantage of ISE-SON over the conventional ISE and SON is because of the dielectric isolation provided by the dielectric pillars and the buried oxide layer except the uppermost part of the channel at which the inversion layer is formed.…”

Section: Introductionmentioning

confidence: 99%

Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Volatge Digital Applications

Kumari¹,

Saxena²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

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Scalable high-speed analog circuit design

Vertregt¹,

Scholtens²

2003

Analog Circuit Design

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Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

Cited by 84 publications

References 13 publications

Recent developments in deca-nanometer vertical MOSFETs

Recent developments in deca-nanometer vertical MOSFETs

Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Volatge Digital Applications

Scalable high-speed analog circuit design

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