No abstract

No abstract

High-speed flash analog-to-digital converters (ADC) are used for read channels in optical and magnetic data storage systems and as building blocks for other ADC architectures such as two-step and pipelined ADCs. To avoid a high-speed digital data bus between converter and DSP IC, both have to be integrated into the same CMOS technology. The threshold voltage mismatch is the most important technology limitation of a flash ADC design.A popular technique for reducing the offsets of the amplifiers is averaging, first introduced by Kattman and Barrow [1], ( Figure 10.2.1). The outputs of the amplifiers OA -,A 1 ...A 9 ,OA + are interconnected via averaging resistors, R 2 . The offset reduction is a function of the ratio between these averaging resistors and the output impedance, R 1 , of the amplifiers. Without averaging, the zero crossing of the outputs, drawn as X OA1-, X A1 , X A2 etc., keep pace with the zero crossings of the input voltage with the accompanying reference voltage. Adding averaging resistors R 2 reduces the offset but also introduces a shift of the output zero crossings (X' OA1 , X' A1 , X' A2 ). This effect deteriorates the integral linearity at the edge of the range of the ADC.

This paper focuses on several methods to save power consumption in mismatch limited ADC designs, like flash and folding architectures. Migrating existing designs to a next submicron technology helps to reduce the power consumption significantly. It is shown that decreasing bandwidth and sample rate creates a more than linear reduction of the power consumption. Both of these methods will be addressed in this paper. Also the balance between power consumption of the analog and digital circuitry will be examined. An existing 6-bit 1.6GS/s ADC in 0.18µm CMOS is transferred to a 0.12µm technology. The sampling rate is reduced to 260MS/s, the measured ERBW to 124MHz while running at only 32mW. As the bandwidth is downscaled 5×, the power consumption is reduced by 10×, which results in an improved conversion efficiency. As the design topology is unaltered, the implemented design sets a reference for evaluation of any low-power technique.

No abstract