A 6b 1.6GSample/s flash ADC in 0.18μm CMOS using averaging termination

Scholtens, P.C.S.; Vertregt, M.

doi:10.1109/isscc.2002.992177

Cited by 8 publications

(3 citation statements)

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“…Figure 11 ISSCC are also indicated [14,[17][18][19][20][21][22][23]. Note that performance approaching this work has only been achieved in CMOS technologies using heavily interleaved pipeline ADCs, which then results in extensive timing calibration between the individual banks.…”

Section: Resultsmentioning

confidence: 99%

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Advances in High-Speed Adc Architectures Using Offset Calibration

Taft¹,

Menkus²,

Tursi³

et al.

Analog Circuit Design

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This paper describes how offset calibration can be used to enhance the speed-resolution performance of ADCs while maintaining low levels of power dissipation. After selecting a high-speed ADC topology, we will justify the need for offset calibration and then present a brief overview of different ADC calibration topologies, indicating their relative merits and drawbacks. We will then describe in more detail how one-time foreground calibration was used to achieve a 0.18 µm CMOS, 1.8V, 1.6GS/s, 8b folding-interpolating ADC with 7.26 ENOB at Nyquist, which only dissipates 774 mW.

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Section: Resultsmentioning

confidence: 99%

“…Measured ENOBs versus F IN at 1.6 GS/s. The near Nyquist performance for CMOSADCs recently published at ISSCC are also indicated[14,[17][18][19][20][21][22][23].…”

mentioning

confidence: 99%

Advances in High-Speed Adc Architectures Using Offset Calibration

Taft¹,

Menkus²,

Tursi³

et al.

Analog Circuit Design

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“…High-speed ADCs are dominated by flash or folded architecture [1], [2]. For their exponential growth of complexity and parallel conversion, both approaches consume much power and occupy more chip area.…”

Section: Introductionmentioning

confidence: 99%

A Linear-Approximation Technique for Digitally-Calibrated Pipelined A/D Converters

Shen

Lee

2005 IEEE International Symposium on Circuits and Systems

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Open-loop amplifiers enrich high-speed capability of pipelined analog-to-digital converters (ADCs). Because both finite gain and circuit nonlinearity limit the accuracy of this approach, a linear-approximation calibration technique is proposed to compensate such non-ideal effects. Due to the nature of two phase requirements, double sampling technique is applied to achieve continuous-time on-line calibration without interrupting the normal data conversion. Pushing the complexity of calibration into the digital domain relaxes the stringent design requirements of analog circuits.

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