A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination

Abstract

High-speed flash analog-to-digital converters (ADC) are used for read channels in optical and magnetic data storage systems and as building blocks for other ADC architectures such as two-step and pipelined ADCs. To avoid a high-speed digital data bus between converter and DSP IC, both have to be integrated into the same CMOS technology. The threshold voltage mismatch is the most important technology limitation of a flash ADC design.A popular technique for reducing the offsets of the amplifiers is averaging, first introduced by Kattman and Barrow [1], ( Figure 10.2.1). The outputs of the amplifiers OA -,A 1 ...A 9 ,OA + are interconnected via averaging resistors, R 2 . The offset reduction is a function of the ratio between these averaging resistors and the output impedance, R 1 , of the amplifiers. Without averaging, the zero crossing of the outputs, drawn as X OA1-, X A1 , X A2 etc., keep pace with the zero crossings of the input voltage with the accompanying reference voltage. Adding averaging resistors R 2 reduces the offset but also introduces a shift of the output zero crossings (X' OA1 , X' A1 , X' A2 ). This effect deteriorates the integral linearity at the edge of the range of the ADC.

A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique

“…The DNL is ±0.15 LSB. This is the lowest DNL achieved in a CMOSbased high speed ADC [6,8]. The interpolator section in this ADC has a bandwidth of 750 MHz, occupies an active area of 0.13 mm 2 and consumes 122-mA current from a 1.8-V power supply.…”

“…In order to maintain the same common mode at all interpolator cell outputs and to equalize the path delays of interpolated and non-interpolated signals, the input pairs of IAMP n−2 , IAMP n and IAMP n+2 are connected together. Averaging resistors (Ravg) are used to reduce the effects of device mismatches, as demonstrated by [8]. Besides that, advanced circuit layout techniques such as gate-aligned and commoncentroid are used to ensure device symmetry.…”

“…Averaging is the most common technique used to reduce offset errors [1,5,8,11]. This technique has been used to improve static errors induced due to amplifiers' offset error.…”

“…The Preamplifier stage generates an amplified output depending on the difference between the input and the reference voltage. The outputs of the Preamplifier stage are passed to an averaging network [5,8], which helps reduce the offset errors.…”

“…This work attempted to overcome the demerits of pure Flash architecture by combining flash and interpolation architecture to achieve the hybrid performance of both with the aid of active interpolator circuit for better linearity compared to the work by [2,6,8,9] and enhanced technique to remove the metastability errors in the Error Correction Circuitry. Using interpolation with Flash has reduced the large non-linear capacitive load at the analog input due to the reduced number of Preamplifiers in the first stage [2].…”