Systematic power reduction and performance analysis of mismatch limited ADC designs

Scholtens, P.C.S.; Smola, David; Vertregt, M.

doi:10.1145/1077603.1077622

Cited by 6 publications

(4 citation statements)

References 12 publications

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“…In the analysis the architecture described in section II is assumed; for this architecture we have implementations in 3 CMOS technologies to support the theoretical finding. The implementations in CI30 and CI80 technologies were published in [8] respectively [3]. This paper presents a very efficient implementation in C045, see sections II and IV.…”

Section: O5vf)f)mentioning

confidence: 99%

“…The crown marked C045 is the system presented here including full optimization and innovations in digital and comparators. The other 2 crowns are the same system , without these optimization and innovations, in CI30 and CI80 [8,3]. Crosses (X) represent non-calibrated flash ADCs and plusses (+) calibrated flash ADCs in literature [1, 2,9].…”

Section: Scaling Analysismentioning

confidence: 99%

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A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

Veldhorst

Goksun

Annema

et al. 2009

2009 Proceedings of ESSCIRC

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Abstract-. A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design . I.INTROD UCTIO N Power-efficient WPAN applications push the demand for high-sp eed low-power wideband flash ADCs. Low resolution ADCs with off-chip calibration show efficiencies better than O.2pJ/conv-step at sampling-rates above IGs/s [I]. However, the energy consumed to perform and sustain this calibration is commonly not accounted for. The non-calibrated flash ADC in standard 45nm CMOS technology reported here demonstrates an energy efficiency comparable to that of a recent onchip calibrated flash ADC in 65nm CMOS [2]. Section II gives an overview of the architecture of the reported system. Section III links the efficiency of the preamplifier to transistor properties and comments on the efficiency improvement obtained. Section IV gives measurements results. II.ARCHITECTURE

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Section: O5vf)f)mentioning

confidence: 99%

Section: Scaling Analysismentioning

confidence: 99%

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

Veldhorst

Goksun

Annema

et al. 2009

2009 Proceedings of ESSCIRC

Self Cite

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“…14 shows a comparison of our estimated performance with experimental data. For the silicon prototype that is currently being implemented, we project an effective number of [25], 248 MS/s and 6-bit [26]), we expect to demonstrate an approximate 2x improvement in conversion efficiency as quantified by the following figure of merit (FOM): (14) VI. CONCLUSION The proposed ADC calibration enables the use of energy efficient SAR ADCs in a time-interleaved, high-speed converter array for an UWB OFDM application.…”

Section: Complexity and Power Estimatesmentioning

confidence: 99%

System embedded ADC calibration for OFDM receivers

Murmann

2006

IEEE Trans. Circuits Syst. I

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This paper describes a background calibration technique for analog-to-digital converters (ADCs) that exploits communication protocol redundancy to measure and correct for analog circuit imperfections. In particular, we consider the implementation of a 6-bit, 500-MS/s ADC in the receiver of an ultra wideband system using orthogonal frequency division multiplexing (OFDM). The calibration is intended for a time-interleaved array of successive approximation register ADCs and cancels converter nonlinearity due to inter-channel offset mismatches. The individual channel offsets are estimated through statistical correlation, based on known pseudorandom modulation sequences used in OFDM pilot tones. Our simulation results show that the proposed calibration is capable of improving the signal-to-noise and distortion ratio from 20 to 37 dB with a tracking time constant of 85 ms, assuming an additive white Gaussian noise channel with 20-dB signal-to-noise ratio.

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“…That will cause high power consumption. To save the power consumption, a quite amount of power reduction techniques have been published for flash ADC, such as folding and interpolating [5], pipelined look-ahead architecture [6], distortion correction [7] and so on [8][9][10]. The authors have also proposed a bisection method to reduce the number of comparators working in every clock cycle [11], to avoid the unnecessary power consumption.…”

Section: Introductionmentioning

confidence: 99%

An efficient power reduction technique for CMOS flash analog-to-digital converters

Hwang

Huang

Hwang

et al. 2009

Analog Integr Circ Sig Process

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An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 lm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 9 0.9 mm 2 without I/O pads.

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Systematic power reduction and performance analysis of mismatch limited ADC designs

Cited by 6 publications

References 12 publications

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

System embedded ADC calibration for OFDM receivers

An efficient power reduction technique for CMOS flash analog-to-digital converters

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