A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

Abstract

Abstract-. A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design . I.INTROD UCTIO N Power-efficient WPAN applications push the demand for high-sp eed low-power wideband flash ADCs. Low resolution ADCs with off-chip calibration show efficiencies better than O.2pJ/conv-step at sampling-rates above IGs/s [I]. However, the energy consumed to perform and sustain this calibration is commonly not accounted for. The non-calibrated flash ADC in standard 45nm CMOS technology reported here demonstrates an energy efficiency comparable to that of a recent onchip calibrated flash ADC in 65nm CMOS [2]. Section II gives an overview of the architecture of the reported system. Section III links the efficiency of the preamplifier to transistor properties and comments on the efficiency improvement obtained. Section IV gives measurements results. II.ARCHITECTURE

A 6bit, 7mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

“…As shown in Table 2, the proposed ADC consumes less power than other ADCs except [7] and [8]. [2] and [3] achieved high speed operation; however, they have large power dissipations due to use of the flash architecture. [17] also achieves high speed operation; however, the power dissipation is also large.…”

“…Conventionally, the flash architecture has been used for these targets because of an advantage to high speed operation [1]. However, the flash architecture has an essential limitation in reducing conversion energy [2], [3]. An open-loop pipelined ADC has been investigated to attain this target [4], however the power dissipation is still large.…”