System embedded ADC calibration for OFDM receivers

Oh, Yangjin; Murmann, Boris

doi:10.1109/tcsi.2006.879063

Cited by 28 publications

(6 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section, we will confirm the correctness of the obtained BER expressions in a Rayleigh channel by comparing (18) with MC simulations for a variety of constellations and mismatch levels. Further, in our simulations, we assume that all sub-carriers are data-modulated (i.e., N=Nd), and the sampling time Ts and the symbol energy Es are normalized.…”

Section: Ber Expression Validationmentioning

confidence: 58%

“…where, z   indicates the largest integer smaller than z. Furthermore, 𝑒𝑟𝑓𝑐(𝑧) in ( 16) is the complementary [27], this integral can be further simplified as (18): 18) grants us to efficiently assess the system performance in the presence of TI-ADC timing mismatch. As a result, this will avoid a demand of very time-consuming MC simulations to evaluate system performance.…”

Section: Ber Derivation By Using Gaussian Approximationmentioning

confidence: 99%

“…Typically, we have 𝛾 ̃𝑅% < 𝛾 𝑅 %. Considering (18), to assure error floors to be lower than 𝐵𝐸𝑅 𝑡 at SNRs, we consider the dominating BER terms only, i.e., ≤ 𝐵𝐸𝑅 𝑡 (20) where, 𝐵 =…”

Section: An Identification Of Tolerable Timing Mismatch Levelsmentioning

confidence: 99%

“…Over the past decades, timing mismatch's impact and its calibrations were fully researched for singlecarrier communication systems [6]- [17]. In recent past, when OFDM was employed in THz communication systems, this issue has been examined for multi-carrier communication systems, and it was shown that the timing mismatch affects OFDM system performance in a different behavior as compared to single-carrier communication systems [18]- [23]. To the best of our knowledge, the impact of timing mismatch on bit error rate (BER) performance in OFDM systems was investigated by simulation only in most studies, which can be very time consuming.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An identification of the tolerable time-interleaved analog-to-digital converter timing mismatch level in high-speed orthogonal frequency division multiplexing systems

Huynh

Mai

Ngoc

et al. 2022

IJECE

View full text Add to dashboard Cite

<span>High-speed Terahertz communication systems has recently employed orthogonal frequency division multiplexing approach as it provides high spectral efficiency and avoids inter-symbol interference caused by dispersive channels. Such high-speed systems require extremely high-sampling <br /> time-interleaved analog-to-digital converters at the receiver. However, timing mismatch of time-interleaved analog-to-digital converters significantly causes system performance degradation. In this paper, to avoid such performance degradation induced by timing mismatch, we theoretically determine maximum tolerable mismatch levels for orthogonal frequency division multiplexing communication systems. To obtain these levels, we first propose an analytical method to derive the bit error rate formula for quadrature and pulse amplitude modulations in Rayleigh fading channels, assuming binary reflected gray code (BRGC) mapping. Further, from the derived bit error rate (BER) expressions, we reveal a threshold of timing mismatch level for which error floors produced by the mismatch will be smaller than a given BER. Simulation results demonstrate that if we preserve mismatch level smaller than 25% of this obtained threshold, the BER performance degradation is smaller than 0.5 dB as compared to the case without timing mismatch.</span>

show abstract

Section: Ber Expression Validationmentioning

confidence: 58%

Section: Ber Derivation By Using Gaussian Approximationmentioning

confidence: 99%

Section: An Identification Of Tolerable Timing Mismatch Levelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An identification of the tolerable time-interleaved analog-to-digital converter timing mismatch level in high-speed orthogonal frequency division multiplexing systems

Huynh

Mai

Ngoc

et al. 2022

IJECE

View full text Add to dashboard Cite

show abstract

“…Therefore, any comparison between different architectures from power consumption viewpoint can-not be fairly accomplished without comparing their linearity performances. The standard deviations of the INL and the DNL determine the parameters of INL-yield and DNL-yield, important in many applications [9].…”

Section: Iidac Architecturesmentioning

confidence: 99%

Analysis and Design of Capacitive DAC Array Switching Scheme for SAR ADC in Low Power Applications

Salih¹,

Renjith.²

2016

IJAREEIE

View full text Add to dashboard Cite

Successive-approximation ADCs (SA-ADCs) have found a wide range of applications requiring low speed and moderate resolution, very-high speed and low resolution or even high speed and high resolution Low-power SA-ADCs have been widely used in low-speed biomedical applications with a limited power budget.Several attempts have been reported in order to reduce the power consumption of the ADC with an emphasis on the employed capacitive DAC. In this paper, both the capacitive digital-to-analog converter (DAC) and the comparator are modified from the typical structure. The conventional structure of an SA-ADC, consists of a sample-and-hold (S/H) circuit, a comparator, a successive approximation register (SAR), and a digital-to-analog converter (DAC).Among them DAC has greater importance, which consumes major power in the ADC module.So by careful designing of DAC module its possible to reduce the power consumption to a great extend. By modifying the existing Conventional DAC architecture, ,its found that the power consumption of the DAC is significantly reduced.In the exsiting Conventional DAC power consumption is found to be about 12mW. But in modified architecture power consumption is reduced to 7mW.So it is stated that by using modified DAC module its possible to work the ADC in low power applications

show abstract

Design of Low Power SAR ADC with Two Different DAC Structure and Two Different SAR Logic Designs and Their Comparisons

Chirapangi¹,

Madhuri²,

Burri³

et al. 2019

Advances in Intelligent Systems and Computing

View full text Add to dashboard Cite

System embedded ADC calibration for OFDM receivers

Cited by 28 publications

References 21 publications

An identification of the tolerable time-interleaved analog-to-digital converter timing mismatch level in high-speed orthogonal frequency division multiplexing systems

An identification of the tolerable time-interleaved analog-to-digital converter timing mismatch level in high-speed orthogonal frequency division multiplexing systems

Analysis and Design of Capacitive DAC Array Switching Scheme for SAR ADC in Low Power Applications

Design of Low Power SAR ADC with Two Different DAC Structure and Two Different SAR Logic Designs and Their Comparisons

Contact Info

Product

Resources

About