A 1.6 GS/s, 16 times interleaved track &amp; hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]

Louwsma, S.M.; Tuijl, E.J.M. van; Vertregt, M.; Scholtens, P.C.S.; Nauta, Bram

doi:10.1109/esscir.2004.1356688

Cited by 11 publications

(13 citation statements)

References 5 publications

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“…A trade-off exists between this factor and the power required for a buffer driving the input load. Here a moderate interleaving factor of 16 is chosen based on the interleaved T/H presented in [3]. In this design an improved version is used which has more bandwidth, includes bootstrapping of the sampling switch for enhanced linearity and includes gain and offset calibration.…”

Section: Architecturementioning

confidence: 99%

A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 ¿m CMOS

Louwsma

Tuijl

Vertregt

et al. 2007

2007 IEEE Symposium on VLSI Circuits

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It consists of an interleaved T/H section. a first SA-ADC, a A time-interleaved ADC is presented with 16 channels, DAC, an inter-stage amplifier and a second SA-ADC. Both each consisting of two Successive Approximation (SA) ADCs SA-ADCs ar 6 bit and With the (amplifier gain of 16 the in a pipeline configuration. Three techniques are presented to resolution becomes 10 bit. Pipelining an:d inter-stage gain increase the speed of arn SA-ADC. Sinlgle channel relaxes the requirements of the SA-ADC:s: more time is perfoance is 6.9 ENOB at an inlput frequency of 4 GHz. available per conversion anid the required accuracy is reduced.Multi-channel perfomiance is 7.7 ENOB at 1.35 GS/s with anlThe inter-stage amplifier uses a sxitched-capacitor opalmp ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.configuLration witxih offset cancellation of the two-stage opamp.

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Section: Architecturementioning

confidence: 99%

A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 ¿m CMOS

Louwsma

Tuijl

Vertregt

et al. 2007

2007 IEEE Symposium on VLSI Circuits

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“…6) and an evaluation board have been used for testing. Next to the scrambling hardware, the ADC front-end uses a 16-times interleaved sampler, low-jitter clocking and high linearity buffer techniques just as in [3] to allow high-frequency testing and a switching matrix similar to [4], allowing simultaneous subsampled measurement of 2 slices using 2 ADCs. The ADCs are library IP blocks.…”

Section: Test Setup Details and Measurement Resultsmentioning

confidence: 99%

A narrow-to-wideband scrambling technique increasing software radio receiver linearity

Houwelingen

Tuijl

Nauta

et al. 2011

2011 Proceedings of the ESSCIRC (ESSCIRC)

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Radio receivers and transmitters produce distortion products which are high above the noise floor. These products emanate from a combination of a low-order nonlinearity and the narrowband nature of the signal of interest. In this work, a scrambling system is proposed that can be added to a receiver, reducing these distortion products. Continuous time-domain signal manipulation is used to spread the spectral power of a narrowband signal, before it passes through nonlinear receiver circuitry. Digitally the original signal shape is reconstructed. This way, the distortion created by the nonlinearity does not result in dominant tones, improving IP2 and IP3 figures without increasing the intrinsic circuitry linearity, saving power and maintaining flexibility. This topology became possible through using new designs and topologies, which allow signal manipulation using passive components only. Additionally, a new high speed DAC design allows a voltage supply rail to be used as a sub-mV accurate reference. The concept is demonstrated using a software-radio approach, in which the sampling and buffering represents the nonlinear processing. With a 2.2V pp,diff 100 MHz input signal, the measured distortion products are below -74 dBc. At 1.4 GHz input this number is 60.2 dBc. The scrambling hardware uses 54 mW in a 65nm CMOS process.

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“…In summary, only five transistors (MN1, NM2, NM3, MP1 and main switch) cause timing skews. Besides, matched lines in the layout are used (same width, length and spacings) to distribute clock and input signals to the channels [10]. The post-simulated variation of time skew from 500 Monte Carlo is 500 fs.…”

Section: Proposed Adc Architecturementioning

confidence: 99%

A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS

Zhu

Zhou

et al. 2017

IEICE Electron. Express

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This paper presents an 8-channel time-interleaved SAR ADC. A novel sampling structure is proposed to improve the input bandwidth which also avoids time-skew calibration. The comparator offset cancellation is achieved by body voltage adjustment using low-power charge pump. Each channel has its own on-chip reference buffer to stable reference voltage and correct gain mismatches. The prototype is fabricated in 1P6M 0.13 µm CMOS technology. At 400 MS/s, the ADC achieves an SNDR of 50.84 dB and 45.7 dB at 19.1 MHz and 451 MHz, respectively. It consumes 200 mW, resulting in FOM of 1.76 pJ/con-step.

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A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]

Cited by 11 publications

References 5 publications

A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 ¿m CMOS

A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 ¿m CMOS

A narrow-to-wideband scrambling technique increasing software radio receiver linearity

A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS

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