Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices

Kimbrough, Joevonte; Williams, L.; Yuan, Qunying

doi:10.3390/mi12010012

Cited by 8 publications

(8 citation statements)

References 48 publications

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“…In the rotational motion, the angular velocity of a CNT in an electrical field is described by equation (20) [93]…”

Section: Carbon Nanotube Velocity In Mediumsmentioning

confidence: 99%

“…Although a high yield was obtained, the variation in the resistance in 7465 CNTFET devices was between 100 k Ohm and 10 M Ohm. Kimbrough et al employed the DEP force in the fabrication of wafer-scale CNTFETs, as shown in figure 15(f) [20]. The yield of the functional devices was 87%, with 30% having I DS on/off current ratio larger than 20, while the remaining devices had I DS on/off current ratio less than 20.…”

Section: Cnt-based Transistorsmentioning

confidence: 99%

“…DEP is commonly utilized in manipulating CNT because of its compatibility with other fabrication processes and better control of the CNT density. DEP can also be conducted at room temperature, which provides high flexibility in terms of hardware setup [20]. There are three main components that control the DEP outcomes: the electrode configuration, medium properties, and the supplied AC signal [21][22][23].…”

Section: Introductionmentioning

confidence: 99%

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Dielectrophoretic alignment of carbon nanotubes: theory, applications, and future

2023

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Carbon nanotubes (CNTs) are nominated to be the successor of several semiconductors and metals due to their unique physical and chemical properties. It has been concerning that the anisotropic and low controllability of CNTs impedes their adoption in commercial applications. Dielectrophoresis (DEP) is known as the electrokinetics motion of polarizable nanoparticles under the influence of non-uniform electric fields. The uniqueness of this phenomenon allows DEP to be employed as a novel method to align, assemble, separate, and manipulate CNTs suspended in liquid mediums. This article begins with a brief overview of CNT structure and production, with the emphasize on their electrical properties and response to electric fields. The DEP phenomenon as a CNT alignment method is demonstrated and graphically discussed, along with its theory, procedure, and parameters. We also discussed the side forces that arise in DEP systems and how they negatively or positively affect the CNT alignment. The article concludes with a brief review of CNT-based devices fabricated using DEP, as well as the method’s limitations and future prospects. 

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“…In the rotational motion, the angular velocity of a CNT in an electrical field is described by equation (20) [93]…”

Section: Carbon Nanotube Velocity In Mediumsmentioning

confidence: 99%

Section: Cnt-based Transistorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dielectrophoretic alignment of carbon nanotubes: theory, applications, and future

2023

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“…Recently, Carbon Nanotubes (CNTs) have come to the fore as most promising materials and are being considered for a wide variety of applications ranging from large-scale structure to nanometer-scale electronics because of their superior mechanical and physical properties [32,33]. CNTs were discovered accidentally by Japanese physicist S. lijima [34] in 1991 when performing experiments on carbonium.…”

Section: A Brief On Carbon Nanotube Field Effect Transistors (Cntfets)mentioning

confidence: 99%

Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)

et al. 2021

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Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.

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“…density and the degree of order), which in turn will greatly affect the conductivity of the transistor. Limited by the poor purification technology of sc-SWCNT, early dielectrophoresis reports on low purity sc-SWCNTs dispersion generally had very low on/off current ratios and poor device performace of FETs [23,24], just because m-SWCNTs would suffer a larger dielectrophoretic force (F DEP ) than sc-SWCNTs under an ununiform electric field, leading a preferential collection and arrangement of the m-SWCNTs in the channel to the sc-SWCNTs. As a result, dielectrophoresis method was ever used to effectively separate m-SWCNTs from a mixed SWCNTs [25].…”

Section: Introductionmentioning

confidence: 99%

Single layer aligned semiconducting single-walled carbon nanotube array with high linear density

Líu¹,

Liu²,

Sun³

et al. 2022

Nanotechnology

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Highly ordered semiconducting single-walled carbon nanotubes(sc-SWCNTs) array with high purity, high linear density and controllable manner is strongly desired for carbon-based integrated circuits, yet it remains a big challenge. Herein, close-packed single layered and controllably aligned sc-SWCNTs arrays were obtained through dielectrophoresis using a high purity sc-SWCNT dispersion. Under optimized condition of length and average number of interconnecting junctions across the channel full of aligned sc-SWCNTs, field effect transistors (FETs) with high performance were achieved with both a high on/off current ratio and large carrier mobility. Based on the optimized channel length, by systematically optimizing the dielectrophoresis parameters of the frequency and duration of applied AC voltage (Vpp), the highly ordered sc-SWCNTs arrays with an ultra-high linear density of 54±2 tubes/μm showed relatively high device performance of FET. The fabrication process optimized in this report can be further extended and applied in large-area, low-cost carbon-based integrated circuits.

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Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices

Cited by 8 publications

References 48 publications

Dielectrophoretic alignment of carbon nanotubes: theory, applications, and future

Dielectrophoretic alignment of carbon nanotubes: theory, applications, and future

Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)

Single layer aligned semiconducting single-walled carbon nanotube array with high linear density

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