Differential register allocation

Abstract

Micro-architecture designers are very cautious about expanding the number of architected registers (also the register field), because increasing the register field adds to the code size, raises I-cache and memory pressure, complicates processor pipeline. Especially for low-end processors, encoding space could be extremely limited due to area and power considerations. On the other hand, the number of architected registers exposed to the compiler could directly affect the effectiveness of compiler analysis and optimization. For high performance computers, register pressure can be higher than the available registers in some regions, e.g. due to optimizations like aggressive function inlining, software pipelining etc. The compiler cannot effectively perform compilation and optimization if only a small number of registers are exposed through the ISA. Therefore, it is crucial that more architected registers are available at the compiler's disposal without expanding the code size significantly.In this paper, we look at a new register encoding scheme called differential encoding that allows more registers to be addressed in the operand field of instructions than the direct encoding currently being used. We show it can be implemented with very low overhead. Based upon differential encoding, we apply it in several ways such that the extra architected registers can benefit the performance. Three schemes are devised to integrate differential encoding with register allocation. We demonstrate that differential register allocation is helpful in improving the performance of both high-end and low-end processors. Moreover, We can combine it with software pipelining to provide more registers and reduce spills.Our results show that differential encoding significantly reduces the number of spills and speeds up program execution. For a lowend configuration, we achieve over 12% speedup while keeping code size almost unaffected. For optimization on loops, it significantly speeds up loops with high register pressure (over 70% speedup).

Doubling the number of registers on ARM processors

“…Differential Register Allocation can also double the number of registers, but the mechanism is different [16]. It encodes the register field using the difference between consecutive register accesses to allow the compiler to allocate more registers than can be specified using a regular encoding, while this work uses the underutilized condition bits to double the number of architectural registers.…”

“…The number of architectural registers exposed to the compiler and the programmer is crucial to the code quality, as a small number of architectural registers might restrict compilers from effectively performing compilation and optimization or prevent programmers from storing some frequently used data [16]. Therefore, it is critical that more architectural registers are available to the compiler and programmer without expanding the code size significantly.…”

“…If every instruction is stretched from 32 bits to 36 bits in order to accommodate these extra bits, the code size would increase by about 12% on the 32-register ARM. In addition, widened instructions would intensify the I-cache and memory traffic, and hence bump up the power consumption [15], [16].…”

Allocating architected registers through differential encoding

“…A preliminary version of this article will appear in the Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation (PLDI 2005) [Zhuang and Pande 2005]. We would like to thank anonymous PLDI referees for their comments and suggestions and also Mr. Josh Fryman from Georgia Tech for his help on the architecture side.…”

Efficient Use of Invisible Registers in Thumb Code

“…Our approach is also more flexible than register windows because it allows various subsets of 8 registers to be active. Differential Register Allocation [15] proposes encoding the register specifier using the difference between consecutive register accesses, allowing the compiler to allocate more registers than can be specified using a regular encoding. This scheme, unlike ours, does not provide backward compatibility of binaries.…”