This presentation will focus on using microarray data on a clonal osteoblast cell model to analyze the early BMP-2 responsive genes, as well as some of the later genes regulated by BMP2 during different phases of mineralization. We will focus on the early phases of gene expression that occur after BMP2 signaling from 30 min up to 1 day. The hypothesis is that understanding how these early genes are regulated during the initial multilayering and growth phase of osteoblasts will lead to models of how BMP activity stimulates cell growth, cell migration, multilayering, matrix deposition and remodeling phase that allows subsequent mineralization. The Dlx2 and Dlx5 homeobox genes have been shown to be critical for bone formation both in vitro and in vivo. Both Dlx 2 and Dlx5 are activated within 15-30 minutes after BMP2 addition to the mouse 2T3 osteoblast model and primary fetal rat calvarial osteoblasts. The Dlx2 and Dlx5 genes stay elevated in the presence of BMP2 for up to 5 days, a time when overt mineralization is just beginning. To understand the genomic network that Dlx5 and Dlx2 regulate at the transcription level, we have taken an approach where we use a specific transcription repressor protein, Engrailed, ligated to the Dlx5 homeodomain. The idea is that this Eng-Dlx5 protein will interact with Dlx5 and possibly Dlx2 and related Dlx- regulated genes in vivo and down-regulate their transcriptional initiation. Using a microarray approach with over 5,000 known genes we can identify the genes that are directly and indirectly regulated by Dlx5 and Dlx2. This will allow us to build an initial genomic network of Dlx- regulated genes at the transcriptional level. We will present our model and preliminary efforts at understanding the genomic network regulated by this important BMP2-regulated transcription factor class in osteoblast biology.

No abstract

No abstract

A pplications written for the embedded domain must perform under the constraints of limited memory and limited energy. While these constraints have always existed, current trends, such as mobile computing and ubiquitous computing, bring more and more complex applications to the embedded domain, making performance, or speed of execution, an important factor as well. For instance, we are now able to run resource-intensive gaming and multimedia applications on handheld devices. Techniques that reduce the memory and energy consumption of programs have in general done so at the cost of performance. Simultaneously achieving small code size, low energy consumption, and high performance is a challenging task.Processors, such as the ARM and MIPS family of embedded cores, support more than one instruction set to meet these constraints. In addition to the 32-bit instruction set, they support a 16-bit instruction set. As we will explain, by using 16-bit code one can achieve code size and energy reduction at the cost of performance.Until recently, the choice between 32-bit and 16-bit code had to be made by the programmer, and is highly undesirable. In this article, we show how this task can be automated and how one can achieve the code-size and energy-saving properties of 16-bit code while simultaneously achieving performance comparable to 32-bit code. We focus on the encoding of a program's computations. This is in contrast to the previous articles in this special section, which primarily focus on the elimination of superfluous computations from a program. The techniques described here are in the context of the ARM family of processors, which are frequently used in the embedded computing realm. They are used as general-purpose embedded processors, found, for example, on multimedia-enabled PDAs, as well as in specialized embedded applications, such as embedded control.ARM processors have a simple energy-efficient architecture. The StrongARM [8],Encoding a program's computations to reduce memory and power consumption without sacrificing performance.

In the embedded domain, memory usage and energy consumption are critical constraints. Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.