Dynamic coalescing for 16-bit instructions

Abstract

In the embedded domain, memory usage and energy consumption are critical constraints. Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

Link-time binary rewriting techniques for program compaction

“…Recently, Krishnaswamy and Gupta [2002] proposed an automated profile-guided technique to select ARM/Thumb code. When combined with Thumb extensions [Krishnaswamy and Gupta 2005] that increase its performance, these techniques can avoid the need to compromise between performance and code size.…”

An emerging adaptive architecture and compilation techniques

“…Since spatial/temporal localities of instructions and interference in the cache [4] play important roles for increasing instruction cache hit rate [5], different organizations and sizes of caches have been employed to improve performance in various systems. Since increasing code density permits the use of a smaller sized cache, code compression [6], instruction coalescing [7], instruction packing [8], and other specific approaches [9] have come into practice. The outcomes of such advancements have decreased power dissipation and increased throughput.…”

Efficient Use of Invisible Registers in Thumb Code

“…Our prior work [6] introduced a dynamic instruction coalescing framework which enabled removal of peephole inefficiencies from Thumb code. The impact of coalescing was to enable translation of a pair of Thumb instructions into a single ARM equivalent at runtime.…”

“…The peephole inefficiency problem has been addressed by developing a dynamic instruction coalescing framework that consists of instruction set, microarchitecture, and compiler support that enables pairs of instructions in Thumb code to be replaced by single ARM instructions [6] . The compiler enables coalescing by generating AXThumb code which is Thumb instructions extended with Augmenting eXtensions (AX).…”

“…The coalescing is performed in a manner that no bubbles in the pipeline are introduced. One could generate a mixed binary using both ARM and Thumb instructions; however, the overhead of explicit switching between 16-bit mode and 32-bit mode for short sequences negates the benefit of mixed code [6].…”