Profile guided selection of ARM and thumb instructions

Krishnaswamy, Arvind; Gupta, Rajiv

doi:10.1145/513829.513840

Cited by 51 publications

(13 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The Thumb version of an application is on average 30% smaller than its 32-bit ARM counterpart [4]. It should be noted that using Thumb code, with every 32 bits fetched, the processor fetches two Thumb instructions.…”

Section: Mixed-widthmentioning

confidence: 99%

See 1 more Smart Citation

Mixed-width instruction sets

Krishnaswamy

Gupta

2003

Commun. ACM

Self Cite

View full text Add to dashboard Cite

A pplications written for the embedded domain must perform under the constraints of limited memory and limited energy. While these constraints have always existed, current trends, such as mobile computing and ubiquitous computing, bring more and more complex applications to the embedded domain, making performance, or speed of execution, an important factor as well. For instance, we are now able to run resource-intensive gaming and multimedia applications on handheld devices. Techniques that reduce the memory and energy consumption of programs have in general done so at the cost of performance. Simultaneously achieving small code size, low energy consumption, and high performance is a challenging task.Processors, such as the ARM and MIPS family of embedded cores, support more than one instruction set to meet these constraints. In addition to the 32-bit instruction set, they support a 16-bit instruction set. As we will explain, by using 16-bit code one can achieve code size and energy reduction at the cost of performance.Until recently, the choice between 32-bit and 16-bit code had to be made by the programmer, and is highly undesirable. In this article, we show how this task can be automated and how one can achieve the code-size and energy-saving properties of 16-bit code while simultaneously achieving performance comparable to 32-bit code. We focus on the encoding of a program's computations. This is in contrast to the previous articles in this special section, which primarily focus on the elimination of superfluous computations from a program. The techniques described here are in the context of the ARM family of processors, which are frequently used in the embedded computing realm. They are used as general-purpose embedded processors, found, for example, on multimedia-enabled PDAs, as well as in specialized embedded applications, such as embedded control.ARM processors have a simple energy-efficient architecture. The StrongARM [8],Encoding a program's computations to reduce memory and power consumption without sacrificing performance.

show abstract

Section: Mixed-widthmentioning

confidence: 99%

“…In some cases it is even slightly smaller due to the improved instruction cache behavior of Mixed Code. A more detailed analysis, including a comparison with three other heuristics, is available in [4].…”

Section: Profile-guided Generation Of Mixed Codementioning

confidence: 99%

Mixed-width instruction sets

Krishnaswamy

Gupta

2003

Commun. ACM

Self Cite

View full text Add to dashboard Cite

show abstract

“…Most THUMB instructions can only access 8 registers although all 16 registers are physically present. The compact THUMB instruction set demonstrates better I-cache power saving but lower performance partially due to the small number of architected regis-ters available [8] 1 . Study in [8] shows that compiling the same program with 16-bit THUMB mode instead of the 32-bit ARM mode can save up to 19% I-cache energy.…”

Section: Introductionmentioning

confidence: 99%

“…Although the hardware can support more registers such as on ARM and MIPS, the ISA bottleneck prevents them from being addressed and utilized. [8] mentions that with a compact ISA (THUMB or MIPS-16), instruction count can increase by 9% to 41%, which not only slows down the execution but eliminates some of the benefits brought about by a compact ISA.…”

Section: Introductionmentioning

confidence: 99%

Differential register allocation

Zhuang

Pande

2005

SIGPLAN Not.

View full text Add to dashboard Cite

Micro-architecture designers are very cautious about expanding the number of architected registers (also the register field), because increasing the register field adds to the code size, raises I-cache and memory pressure, complicates processor pipeline. Especially for low-end processors, encoding space could be extremely limited due to area and power considerations. On the other hand, the number of architected registers exposed to the compiler could directly affect the effectiveness of compiler analysis and optimization. For high performance computers, register pressure can be higher than the available registers in some regions, e.g. due to optimizations like aggressive function inlining, software pipelining etc. The compiler cannot effectively perform compilation and optimization if only a small number of registers are exposed through the ISA. Therefore, it is crucial that more architected registers are available at the compiler's disposal without expanding the code size significantly.In this paper, we look at a new register encoding scheme called differential encoding that allows more registers to be addressed in the operand field of instructions than the direct encoding currently being used. We show it can be implemented with very low overhead. Based upon differential encoding, we apply it in several ways such that the extra architected registers can benefit the performance. Three schemes are devised to integrate differential encoding with register allocation. We demonstrate that differential register allocation is helpful in improving the performance of both high-end and low-end processors. Moreover, We can combine it with software pipelining to provide more registers and reduce spills.Our results show that differential encoding significantly reduces the number of spills and speeds up program execution. For a lowend configuration, we achieve over 12% speedup while keeping code size almost unaffected. For optimization on loops, it significantly speeds up loops with high register pressure (over 70% speedup).

show abstract

“…While the AX extensions described in this paper are for the ARM architecture, the idea of Instruction Coalescing and Augmenting instructions can be applied to other dual width processors. In previous work [6] we showed how one could achieve good code size, low energy and high performance using profile guided heuristics at compile time. The techniques described here are orthogonal to the previous techniques and more scalable.…”

Section: Introductionmentioning

confidence: 99%

Enhancing the performance of 16-bit code using augmenting instructions

Krishnaswamy

Gupta

2003

SIGPLAN Not.

Self Cite

View full text Add to dashboard Cite

In the embedded domain, memory usage and energy consumption are critical constraints. Dual width instruction set embedded processors such as the ARM provide a 16-bit instruction set in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and I-cache energy savings at the cost of performance. We have observed that throughout 16-bit Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed an approach which uses combination of compiler and architectural support to exploit the above property for improving performance of 16-bit code. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). The task of the compiler is to identify pairs of Thumb instructions that can be safely combined and executed as single ARM instructions. The compiler replaces such pairs of Thumb instructions by AX+Thumb instruction pairs. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. Thus, using AX instructions, the compiler can both generate compact 16-bit code and provide hardware with information needed to produce better performing 32-bit code.

show abstract

Profile guided selection of ARM and thumb instructions

Cited by 51 publications

References 1 publication

Mixed-width instruction sets

Mixed-width instruction sets

Differential register allocation

Enhancing the performance of 16-bit code using augmenting instructions

Contact Info

Product

Resources

About