Diffraction Based Overlay Metrology for Double Patterning Technologies

Dasari, Prasad; Li, Jie; Hu, Jiangtao; Smith, Nigel; Kritsu, Oleg

doi:10.5772/21970

Cited by 2 publications

(2 citation statements)

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“…The LELE double patterning technique not only entails more complex process stages, but it also needs tighter overlay control compared to the conventional single pattering [7]. Thus, it is crucial to use advanced overlay metrology methods with very high certainty to ensure the quality of fabricated devices.…”

Section: Diffraction Based Overlay -Dbomentioning

confidence: 99%

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SEM image denoising with unsupervised machine learning for better defect inspection and metrology

Dey

Halder

Khalil

et al. 2021

Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV

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Moore's Law states that transistor density will double every two years, which is sustained until today due to continuous multidirectional innovations (such as extreme ultraviolet lithography, novel patterning techniques etc.), leading the semiconductor industry towards 3 nm node (N3) and beyond. For any patterning scheme, the most important metric to evaluate the quality of printed patterns is edge placement error, with overlay being its largest contribution. Overlay errors can lead to fatal failures of IC devices such as short circuits or broken connections in terms of pattern-to-pattern electrical contacts. Therefore, it is essential to develop effective overlay analysis and control techniques to ensure good functionality of fabricated semiconductor devices. In this work we have used an imec N-14 BEOL process flow using litho-etch-litho-etch (LELE) patterning technique to print metal layers with minimum pitch of 48nm with 193i lithography. Fork-fork structures are decomposed into two mask layers (M1A and M1B) and then the LELE flow is carried out to make the final patterns. Since a single M1 layer is decomposed into two masks, control of overlay between the two masks is critical. The goal of this work is of two-fold as, (1) to quantify the impact of overlay on capacitance and (2) to see if we can predict the final capacitance measurements with selected machine learning models at an early stage. To do so, scatterometry spectra are collected on these electrical test structures at (a) post litho, (b) post TiN hardmask etch, and (c) post Cu plating and CMP. Critical Dimension (CD) and overlay measurements for line/space (L/S) pattern are done with SEM post litho, post etch and post Cu CMP. Various machine learning models are applied to do the capacitance prediction with multiple metrology inputs at different steps of wafer processing. Finally, we demonstrate that by using appropriate machine learning models we are able to do better prediction of electrical results.

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Section: Diffraction Based Overlay -Dbomentioning

confidence: 99%

“…Here R(x 0 , λ) is the reflected spectrum from one target pad as a function of wavelength λ and shift x 0 . In the presence of overlay error (ϵ), the symmetry is broken, and the differential spectrum of two pads is described as follows: the DBO target designed pads [7].…”

Section: Diffraction Based Overlay -Dbomentioning

confidence: 99%