Areas of heavy doping, implantation damage, and lattice strains, which are part of any silicon-integrated circuit device, can provide efficient traps for metals and compete for impurities with intentionally introduced gettering sites. In this article we introduce the concept of competitive gettering between gettering sites and devices and perform modeling of competitive gettering in p/p ϩ epi wafers, wafers with internal gettering sites, and silicon-on-insulator ͑SOI͒ wafers. The impact of the substrate resistivity, density of oxide precipitates, and denuded zone/epi layer width is analyzed for a wide span of cooling ranges. It is found that the major consequence of the effect of gettering by devices is that by the end of cooling, the metal concentration in the device area can substantially exceed its average concentration in the wafer, and device yield could degrade. This can be prevented by optimizing the substrate gettering properties. Although fast cooling rates inherent in rapid thermal processing represent a challenge for gettering, it is shown that optimized gettering can perform well even if the wafer is cooled in a rapid thermal processing system at a rate between 5 and 100 degrees per second. Our modeling results indicate that SOI wafers behave differently than epitaxial or bulk wafers because the buried oxide layer provides a barrier for diffusion of metals between the device area and the substrate. The last section of the article presents an experimental proof of principle of competitive gettering.Gettering has been used in semiconductor processing for over forty years ͑see, for example, Ref. 1͒. The physical principles of gettering are well understood, a high density of precipitation sites or enhanced metal solubility in the gettering layer creates a metal concentration gradient from the near-surface ͑device͒ layer towards the gettering layer, and stimulates diffusion of the dissolved metals to the gettering sites ͑see recent reviews 2-4 for a detailed discussion͒. Although the principle of gettering is simple, its efficiency may vary in a wide range depending on the properties of the gettering layer, initial distribution and concentration of metals in the wafer, the range of temperatures of the thermal processing, and finally, the cooling rate. Due to the complexity of these factors, gettering has always been a practical art, whereby gettering properties of each shipment of wafers were individually tailored to a specific process or customer. Optimization was usually achieved by trying wafers with different properties and different thermal histories ͑or even cut from different parts of the ingot͒ on a production line until the most robust type of wafers was identified.The necessity of fine-tuning the gettering properties of the wafer to individual processes led to customer-tailored wafer specifications. In the last decade, a significant effort was made to engineer processes which allow one to form highly efficient gettering sites independent of the initial wafer properties ͑e.g., magic denuded zones,...