Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs

Mafi, Hamidreza; Yavari, Mohammad; Behzadi, Shadan Sadigh

doi:10.1007/s00034-015-0224-0

Cited by 4 publications

(1 citation statement)

References 19 publications

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“…The normal operation of the pipelined ADCs is interrupted in foreground calibrations while background techniques continuously detects and removes the errors. The most popular digital background calibration methods are categorized into histogram-based (Brooks and Lee, 2008; Gholami and Yavari, 2017), statistical-based (Mafi et al , 2018; Mafi et al , 2016), correlation-based (Panigada and Galton, 2006; Panigada and Galton, 2009) and deterministic (McNeill et al , 2009; Sarkar et al , 2015; Sehgal et al , 2015; Montazerolghaem et al , 2015; Zia et al , 2019). The priority of deterministic techniques over others is the faster calibration time.…”

Section: Introductionmentioning

confidence: 99%

New digital background calibration method for pipelined ADCs

Zia

Farshidi

Kosarian

2020

COMPEL

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Purpose Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs. Design/methodology/approach The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix. Findings Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles. Practical implications The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results. Originality/value The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

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