Digital Bimodal Functions and Digital Physical Unclonable Functions: Architecture and Applications

Xu, Teng; Potkonjak, Miodrag

doi:10.1007/978-3-319-14971-4_3

Cited by 3 publications

(2 citation statements)

References 22 publications

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“…By contrast, a memory-based PUF uses a memory component as an arbiter. A digital PUF can usually be implemented as a field-programmable gate array (FPGA) [27]- [34].…”

Section: ) Digital Pufsmentioning

confidence: 99%

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Kamal

Mureşan

2019

IEEE Access

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An electronic physically unclonable function usually includes an on-chip error-correcting code unit, which is vulnerable to security attacks and adds area, power, and data processing time overheads. This paper proposes a mixed-signal physically unclonable function circuit for authentication purposes, which we call the enhanced capacitive physically unclonable function. It divides the input challenge word over multiple computational groups to decrease processing time, increase security, and eliminate the need for error-correcting code units. Most of the challenge bits control capacitive networks grouped into several capacitive cells, while some are analogized through two digital-to-analog converters. One digital-to-analog converter controls the discharge loads of the capacitive cells; the other controls the reference voltage of comparator units. Each comparator controls a counter that digitizes the discharge time into a response chunk. Most of these counters operate at high frequencies for more precise time-to-digital conversion and are overflown to act as roulettes to promote unpredictability. One counter is not overflown to generate a reference response chunk to support error handling. The design allows for more intrinsic variations throughout the fabrication process, leading to unique response chunks. It applies an expanding challenge-response pair approach, generating a 128-bit response word for a 64-bit challenge word. The capacitive nature of the design supports various security features. Simulating the circuit using 45 nm complementary metal-oxide semiconductor technology resulted in an average power of 921.67 µW, a layout area of 22,470 µm 2 , and an average data processing time of 118 µs.

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“…By contrast, a memory-based PUF uses a memory component as an arbiter. A digital PUF can usually be implemented as a field-programmable gate array (FPGA) [27]- [34].…”

Section: ) Digital Pufsmentioning

confidence: 99%

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Kamal

Mureşan

2019

IEEE Access

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“…They promise to enable qualitatively novel security mechanisms e.g. for authentication and key generation and distribution and have consequently become an important research area of hardware security [17,22,21]. Secure authentication of a chip when its responses are obtained from a remote location, i.e.…”

Section: Introductionmentioning

confidence: 99%

An Arbiter PUF Secured by Remote Random Reconfigurations of an FPGA

Spenke¹,

Breithaupt²,

Plaga³

2016

Lecture Notes in Computer Science

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Abstract. We present a practical and highly secure method for the authentication of chips based on a new concept for implementing strong Physical Unclonable Function (PUF) on field programmable gate arrays (FPGA). Its qualitatively novel feature is a remote reconfiguration in which the delay stages of the PUF are arranged to a random pattern within a subset of the FPGA's gates. Before the reconfiguration is performed during authentication the PUF simply does not exist. Hence even if an attacker has the chip under control previously she can gain no useful information about the PUF. This feature, together with a strict renunciation of any error correction and challenge selection criteria that depend on individual properties of the PUF that goes into the field make our strong PUF construction immune to all machine learning attacks presented in the literature. More sophisticated attacks on our strong-PUF construction will be difficult, because they require the attacker to learn or directly measure the properties of the complete FPGA. A fully functional reference implementation for a secure "chip biometrics" is presented. We remotely configure ten 64-stage arbiter PUFs out of 1428 lookup tables within a time of 25 seconds and then receive one "fingerprint" from each PUF within 1 msec.

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