Digital calibration of delta sigma modulator using variable step size LMS based adaptive line enhancer

4th-Order Switched-Current Multistage-Noise-Shaping Delta-Sigma Modulator With a Simplified Digital Noise-Cancellation Circuit

“…As listed in Table II, those six bits, S6 to S1, are influenced with all inputs, A to E, except for S1 (=1). The digital output word Y(z) is a function of inputs and can be written as S6 = Ʃm (0,2,3,6,7,8,10,11,14,15,18,19,22,26,27,30) (24) S5 = Ʃm (0, 3,6,7,8,11,14,15,18,19,21,22,26,27 The Boolean expression for each output can be minimized using a 5-variable Karnaugh map. Those simplified Boolean expressions of each output can be implemented with NAND gates for the adopted DNCC.…”

“…Those adopted circuits not only minimize the offset current but also improve the linearity [12]. Various digital calibration techniques have been published to extract noise and distortion from desired signals [13], [14]; these techniques can deliver high-SNDR ADCs. As reported in [15], a least mean squares (LMS) algorithmbased adaptive line enhancer can assess a desired signal from an input noise signal by informing DNCC coefficients, leading to an enhancement of SNR by >20 dB.…”

“…,29,30) (25) S4 = Ʃm (0,2,5,7,8,10,13,15,17,19,20,22,25,27,28,30) (26)S3 = Ʃm (0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15) …”

A fast digital calibration algorithm for pipeline ADC

“…Simulation results show that the convergence rate of this method can be improved to million clock cycle magnitudes after improvement from thousand clock cycle magnitude before improvement. Literature [4]- [6] propose a way to calibration the ADC, but it is only used in the Σ-Δ ADC. Literature [7]- [8] propose a digital calibration technique for a cyclic ADC using MOS capacitors which has a large applied voltage dependency but a high capacitance per area.…”