Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., SRAM, DFF, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to address this technical challenge. The key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of "soft maximum". Several circuit examples designed in nanoscale technologies demonstrate that the proposed SSS method achieves superior accuracy over the traditional importance sampling technique when the dimensionality of the variation space is more than a few hundred.

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“…log log maximize 1 . (44) Since the covariance matrix Σ g is positive definite, the optimization in (44) is convex.…”

Section: MCmentioning

confidence: 99%

Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space

Sun

Liu

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…The pull up PMOS transistors are assigned minimum width. The widths of access transistor and pull down NMOS are found by making the read and write noise margins equal [13]. The transistor widths for all the technologies are given in The simulation results show that at 45nm technology node, the performance variation does not improve with increase in L. At 22nm, the variation decreases but is not large enough to bring the 3σ access time less than the nominal.…”

Section: Case Study -6t-srammentioning

confidence: 99%

An analytical approach to efficient circuit variability analysis in scaled CMOS design

Gummalla

Subramaniam

Cao

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ /µ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of V th variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing V th variation.

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“…With advances in Internet of Thing (IoT) applications and the expansion of mobile devices, energy consumption has become a primary focus of attention in integrated circuits design [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. While IoT applications cover a broad range of products from wearable devices, smart houses, automotive devices, smart meters to inspection tools and many others, more than 50% of the market is dominated by battery operated devices.…”

Section: Introductionmentioning

confidence: 99%

0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)

Zangi¹,

Feldman²,

Hadas³

et al. 2018

JLPEA

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An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312 K-80 MHz. A number of unique low voltage digital libraries, comprising of approximately 300 logic cells and sequential elements, were used for the MCU SOC design. On-die silicon sensors were utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions, and also to resolve yield and life time problems, while operating at low voltages. A First Fail (FFail) mechanism, which can be digitally and linearly controlled with up to 8 bits, detects the failing SOC voltage at a given frequency. The core operates between 0.45-1.1 V volts with a direct battery connection for an input voltage of 1.6-3.6 V. Measurement results show that the peak energy efficiency is 18µW/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3-5× improved current/DMIPS (Dhrystone Million Instructions per second) compared to the next best chip.

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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

Cited by 183 publications

References 121 publications

Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space

Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space

An analytical approach to efficient circuit variability analysis in scaled CMOS design

0.45 v and 18 μA/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)

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