Digital logic using molecular electronics

Goldstein, Seth Copen; Rosewater, David Martin

doi:10.1109/isscc.2002.993007

Cited by 25 publications

(11 citation statements)

References 6 publications

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“…The increasing interest in fabricating dense layers of parallel NWs with a sublithographic pitch is motivated by the emergence of the NW crossbar paradigm as a possible architecture for post-CMOS technologies [24]- [26]. The baseline organization of a NW crossbar circuit is depicted in Fig.…”

Section: B Baseline Circuit Architecturementioning

confidence: 99%

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Jamaa

Cerofolini

Micheli

et al. 2011

IEEE Trans. Nanotechnology

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Abstract-In this paper, we demonstrate the ability of the multispacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution andCMOS processing steps. We characterize single spacers operating as poly-Si nanowire field effect transistors . We demonstrate also the possibility to lay a spacer perpendicularly to a set of parallel spacers in a crossbar fashion. The extrapolated cross-point density from the small 4 × 1-array is in the range of 10 10 cm −2 . We discuss the applications of this technique to improve the density of previously reported poly-SiNW memories and as a future framework for nanowire crossbars and decoders. Then we analyze the limitations and costs of the proposed technique.

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Section: B Baseline Circuit Architecturementioning

confidence: 99%

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Jamaa

Cerofolini

Micheli

et al. 2011

IEEE Trans. Nanotechnology

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“…nanoPLA [6,8] architecture is a concept based on semiconducting silicon nanowires (SiNWs) organized in a crossbar fashion with molecular switches at their cross-points. The switches can be programmed in order to perform either signal routing or wired-OR logic function.…”

mentioning

confidence: 99%

Complete nanowire crossbar framework optimized for the multi-spacer patterning technique

Ben-Jamaa

Cerofolini

Leblebici

et al. 2009

Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patterning technique to fabricate nanowire crossbars with a high cross-point density up to 10 10 cm −2 . We propose a novel decoder fabrication method that can be included in a process dedicated to the multi-spacer patterning technique. We address the technology problems consisting in the variability and fabrication complexity at the design level by optimizing the encoding scheme. We show an overall reduction of the variability by 18% and a cancelation of the fabrication complexity overhead.

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“…These devices are characterized by a region of negative resistance in their Figure 3.) Devices with useful Peak-to-valley ratio have been measured at room temperature [7]. These molecules can be used to as the basis of logic families [17,14] or as the core of a molecular latch which also provides signal restoration and I/Oisolation [20].…”

Section: Transistors Diodes and Ndrsmentioning

confidence: 99%

“…To create a complete logic family, signals and their complements are brought into each circuit which produce both the desired functions and their complements. Logic values are restored using molecular latches [20]; which also provide a mechanism for latching values and isolating outputs from one nanoBlock from the inputs to another nanoBlock. The nanoBlocks are grouped together…”

Section: Architecturesmentioning

confidence: 99%