Digital phase‐locked loops with a wide locking range using a fractional divider

Kiyota

2018

In the mobile communication equipment, the clock generator for driving each system is required to have a fast pull‐in time, multiple signals of constant pulse interval, synchronization range, low output jitter, and wide lock‐in range characteristics. In this paper, multiple‐frequency multiphase clock digital‐controlled phased‐locked loop (MC‐DCPLL) is proposed. In this loop, the pulse width error of the multiplied output signal is a time within one phase difference of the multiphase clock regardless of the multiplication ratio. The output jitter in the steady state is always within one phase difference of the multiphase clock. Since it is a control method by dividing ratio changeable type, the lock‐in range is extremely wide. Also, the initial pull‐in time is always completed in one cycle of the input signal without being influenced by the multiplication ratio. It is clarified by theory and simulation that these characteristics can be obtained. From the above, the versatility of the proposed multiple‐frequency MC‐DCPLL is extremely high, and it can be expected to be used for clock sources, and so on, in various mobile communication equipment systems.

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multiple‐frequency digital phase‐locked loop based on multiphase clock divider with constant pulse interval

Kiyota

2018

“…However, these digital PLLs suffer from some drawbacks: for example, the output signal frequency cannot be set much different from the center frequency, the pull-in time is long, and a multiplied output signal cannot be obtained at a constant pulse interval. Various methods have been proposed [4,5] to eliminate these drawbacks, but radical improvement has not been achieved because phase control was based on adding or removing reference clock pulses. In addition, methods using clock recovery circuits or digital phase-frequency comparators have been proposed [6,7].…”

Section: Introductionmentioning

confidence: 99%

A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider

Sasaki

2011

SUMMARYSince phase-locked loops (PLL) are used in the clock extraction of digital communications and high-density digital recording, it is required to have simultaneously low jitter, fast pull-in, and wide lock-in range characteristics. However, in the case of the conventional dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection (PM-DCPLL), the output jitter in the steady state becomes no less than half the pulse width of the base clock controlling the loop, and the upper bound frequency of the lock-in range is limited accordingly. In this paper, we propose a dividing ratio changeable digital phaselocked loop (MC-DCPLL) with low jitter, wide lock-in range, and fast pull-in characteristics using a multiphase clock divider. Since the output jitter of this circuit is one phase difference of the multiphase clock in steady state, the circuit can reduce the output jitter to 1/k of that of a conventional PM-DCPLL when a k phase clock is used. Therefore, the upper bound frequency becomes k times that of a conventional PM-DCPLL. Furthermore, the initial pull-in is completed in one period of the input signal by using the initial pull-in circuit.

“…In order to improve these characteristics, research from various perspectives has been undertaken [1][2][3][4][5]. Improvements in one or two of the three areas have been made, but a circuit that satisfies all three characteristics does not exist.…”

Section: Introductionmentioning

confidence: 99%

A dividing ratio changeable digital PLL based on phase state memory and double clock‐edge detection

Sasaki

2010

SUMMARYIn this paper, we propose a dividing ratio changeable digital phase-locked loop (PLL) based on phase state memory and double clock-edge detection that satisfies the three characteristics of low jitter, wide lock-in range, and fast pull-in at the same time. The counter for the double edge detection of the base clock reduces the circuit scale by using a selector. In the steady state, the output jitter of the proposed digital PLL is always a half pulse width of the base clock regardless of the frequency fluctuation of the base clock. Also, the upper bound frequency of the lock-in range becomes six times that of the conventional dividing ratio changeable PLL, when the permissible output jitter is identical. Furthermore, the fast pull-in is finished in one cycle of the input signal and the pulse width of the multiplication output signal becomes almost constant.