(Digital Presentation) Selective SiGe Vapor Etching Using Br₂ in View of Nanosheet Device Isolation

Abstract

Both forksheet and CFET device layouts contain local dielectric isolation layers to circumvent junction isolation trade-offs which are specific for these designs. Typical fabrication schemes start with the epitaxial growth of complicated SiGe/Si multi stacks with at least two different Ge concentrations where a Ge-rich SiGe layer is later replaced by an isolating dielectric. This work proposes a low temperature Br2-based vapor etching process as an option for the selective SiGe removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etching selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x = 0.2 - 0.3).