Digital signal processing aspects of software definable radios

2006 10th IEEE Singapore International Conference on Communication Systems

Meher

2006

The flexibility of a software-defined radio (SDR) depends on its capability to operate in multi-standard wireless communication environments. The most computationally intensive part of the digital front end of an SDR receiver is the channelizer, which extracts multiple narrowband signals from a wideband input signal. The compatibility of the channnelizer with different communications standard is guaranteed by its reconfigurability. Low power and high-speed are the two other desirable characteristics of a channelizer. This paper presents a combinational architecture based on Discrete Fourier Transform filter bank and Quadrature Mirror filter bank trees for realizing a reconfigurable low complexity high-speed channelizer. Our hybrid channelizer has an additional complexity of 38% over the quadrature mirror filter bank, but the delay of the former is reduced by 94% when compared to the latter. Thus the proposed channelizer architecture offers a better trade-off between the complexity and delay.

Section: Introductionmentioning

confidence: 99%

Reconfigurable Architectures for Low Complexity Software Radio Channelizers using Hybrid Filter Banks

Chang

2006 10th IEEE Singapore International Conference on Communication Systems

Meher

2006

“…It has been shown that the PFP representation can be employed to implement the quadrature mirror filters (QMF) using the lower bound value of 11 bits in [7]. In this paper, we show that the coefficients of the pulse shaping filters can be coded using a wordlength which is considerably lower than conventional 24-bit and 16-bit implementations discussed in [3,4]. The resulting filters can be implemented using fewer number of adders and is ideal for the look-up table implementation due to its low coefficient entropy.…”

Section: Introductionmentioning

confidence: 88%

“…In the case of filter implementation in [3,4], the L and M values of 24-bit fixed-point coefficients are 5 and 23 respectively. Hence, 28 bits are needed by the PFP for general coefficient sets.…”

Section: The Pseudo Floating-point Representationmentioning

confidence: 99%

“…For a multiplierless filter implementation, the hardware complexity increases with the number of the adders, which is proportional to the filter wordlength [2]. The fixed-point arithmetic implementation of channel filters in digital wideband receivers requires 24-bit wordlength to meet the channel specifications [3,4]. It has been reported that the 16-bit implementation results in a significant degradation in stop-band attenuation preventing the required spectral mask requirements from being met [3].…”

Section: Introductionmentioning

confidence: 99%

“…The fixed-point arithmetic implementation of channel filters in digital wideband receivers requires 24-bit wordlength to meet the channel specifications [3,4]. It has been reported that the 16-bit implementation results in a significant degradation in stop-band attenuation preventing the required spectral mask requirements from being met [3]. The entropy of a coefficient is a measure of the information content that can be coded in minimum number of bits.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An optimal entropy coding scheme for efficient implementation of pulse shaping FIR filters in digital receivers

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

Premkumar

Lai

The most computationally intensive part of wide-band receivers is the IF processing block. Digital filtering is the main task in IF processing. Infinite precision filters require complicated digital circuits due to coefficient multiplication. This paper presents an efficient method to implement pulse shaping filters for a dualmode GSM/W-CDMA receiver. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filters can be coded using an optimal entropy scheme employing PFP which requires only considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of GSM/W-CDMA specifications.

An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

Mahesh

2010

J Sign Process Syst

The channelizer in a software defined radio (SDR) base station extracts individual radio channels from the digitized wideband input signal at a very high sampling rate. The base station channelizer must be able to simultaneously extract multiple channels of non-uniform bandwidths corresponding to channel bandwidths of different communication standards. Reconfigurability and low complexity are the two key requirements in the SDR channelizer. A new reconfigurable filter bank (FB) architecture based on interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB can be used for obtaining very narrow passband channels with extremely low complexity. Using a cascaded structure of the proposed FB, it is possible to extract channels of fractional passband widths by changing the interpolation factor. Design example shows that the proposed FB offers complexity reduction of 84% over the conventional per-channel (PC) approach. The proposed FB has been implemented and tested on Xilinx Virtex 2v3000ff1152-4 FPGA. Implementation results show that the proposed FB offers area reduction of 48.37%, speed improvement of 52.7% and power reduction of 75.9% over the PC approach.