Reconfigurable Architectures for Low Complexity Software Radio Channelizers using Hybrid Filter Banks

Abstract

The flexibility of a software-defined radio (SDR) depends on its capability to operate in multi-standard wireless communication environments. The most computationally intensive part of the digital front end of an SDR receiver is the channelizer, which extracts multiple narrowband signals from a wideband input signal. The compatibility of the channnelizer with different communications standard is guaranteed by its reconfigurability. Low power and high-speed are the two other desirable characteristics of a channelizer. This paper presents a combinational architecture based on Discrete Fourier Transform filter bank and Quadrature Mirror filter bank trees for realizing a reconfigurable low complexity high-speed channelizer. Our hybrid channelizer has an additional complexity of 38% over the quadrature mirror filter bank, but the delay of the former is reduced by 94% when compared to the latter. Thus the proposed channelizer architecture offers a better trade-off between the complexity and delay.

Reconfigurable Digital Channelizer Design Using Factored Markov Decision Processes

“…As illustrated in [7,1], the channelizer is often one of the most computationally intensive and power consuming blocks of cognitive radio transceivers, mainly due to its need to run at the highest data rates. For this reason, several researchers have sought to create channelizer designs where the key parameters that control the processing (e.g., filter coefficients, data rates, and subchannel masks) are configurable at run-time [5,6,8]. We refer to this class of DSP systems as "reconfigurable channelizers", and point to this active body of DSP research as evidence for the importance of optimizing channelizer processing for exactly what is required, and nothing more.…”