2018
DOI: 10.1016/j.nima.2017.10.022
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Digital SiPM channel integrated in CMOS 65 nm with 17.5 ps FWHM single photon timing resolution

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Cited by 25 publications
(19 citation statements)
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“…The 1st tier contains SPAD arrays with TSVs for each microcell, the 2nd tier contains the quenching circuit arrays and the 3rd tier contains the advanced signal processing and readout functionalities. First results show a very promising time resolution of this concept integrated in 65 nm CMOS with measured SPTR values of 17.5 ps FWHM (Nolet et al 2018).…”
Section: The Digital Sipmmentioning
confidence: 90%
See 1 more Smart Citation
“…The 1st tier contains SPAD arrays with TSVs for each microcell, the 2nd tier contains the quenching circuit arrays and the 3rd tier contains the advanced signal processing and readout functionalities. First results show a very promising time resolution of this concept integrated in 65 nm CMOS with measured SPTR values of 17.5 ps FWHM (Nolet et al 2018).…”
Section: The Digital Sipmmentioning
confidence: 90%
“…Therefore newer research on the digital SiPM is moving in the direction of 3D assembling of the detector (Bérubé et al 2015, Nolet et al 2018, Nolet et al 2020. In figure 17(b) an example of a 3D integration is shown, that the group from Sherbrooke is currently working on Bérubé et al (2015).…”
Section: The Digital Sipmmentioning
confidence: 99%
“…To conclude, high-frequency readout is one way to reach the limits in timing performance given by modern analog SiPMs, but most likely not the only way. On the other hand, the fully digital SiPM does not struggle with these limitations and will presumably be the best option to achieve the intrinsic timing limits in TOF-PET, given by photostatistics and the photodetector itself, if the detector can be successfully integrated in a scalable 3D design (Nolet et al 2018). .…”
Section: Discussing the Sipm Readoutmentioning
confidence: 99%
“…Since the pixel size is in the order of 50 × 50 µm 2 range and performance under 10 ps is mandatory for some of the aforementioned applications, every individual contribution in timing and size must be optimized. The TDC developed to be integrated in the pixel has a timing jitter of 6.9 ps rms [33] and the first results of a 2D pixel in CMOS 65 nm has a 17.5 ps FWHM SPTR [34]. To obtain a SPAD array with a 10 ps SPTR, the first step is to achieve a single SPAD and quenching circuit that can reach a SPTR of 10 ps.…”
Section: Introductionmentioning
confidence: 99%