Digital subthreshold logic design - motivation and challenges

Fisher, S.; Teman, Adam; Vaysman, Dmitry; Gertsman, Alexander; Yadid-Pecht, Orly; Fish, Alexander

doi:10.1109/eeei.2008.4736624

Cited by 33 publications

(9 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is interesting to note that the same equation describes the subthreshold current of an MOS device taking into account the drain-induced barrier lowering effect. 37 This effect becomes prominent in sub-micron technologies, where the source and drain depletion regions penetrate significantly into the channel and control the potential and the field inside the channel. In our case of all-metallic switches, similar I-V characteristics are observed in the long channel devices.…”

Section: Possible Circuit Applicationsmentioning

confidence: 99%

All-metallic electrically gated 2H-TaSe₂ thin-film switches and logic circuits

Renteria

Samnakay

Jiang

et al. 2014

Journal of Applied Physics

View full text Add to dashboard Cite

We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe 2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear currentvoltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe 2 -Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used in principle for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.

show abstract

Section: Possible Circuit Applicationsmentioning

confidence: 99%

All-metallic electrically gated 2H-TaSe₂ thin-film switches and logic circuits

Renteria

Samnakay

Jiang

et al. 2014

Journal of Applied Physics

View full text Add to dashboard Cite

show abstract

“…Future little, minimal effort satellites have an even lower control financial plan, as the all out satellite weight is regularly diminished by limiting the utilization of substantial batteries and power supplies. The most proficient approach to accomplish ULP operation in incorporated circuits is to forcefully diminish the supply voltage (VDD) what's more, work all segments of the chip near or on the or on subthreshold region [1], [2], in this way fundamentally diminishing both static and dynamic power utilization. The supply voltage can be reduced to the deep sub-threshold region, dramatically saving power in logic and memory.…”

Section: Introductionmentioning

confidence: 99%

An Ultra Low Power Space Application based Radiation-Hardened Low Voltage 4T SRAM Bitcell

Raj¹

2019

IJRASET

View full text Add to dashboard Cite

Continues transistor scaling, exacerbates the situation, as susceptibility to soft-errors is increased in VLSI circuits, particularly when exposed to severe environmental conditions, such as cosmic radiation and charged particles .Silicon covers most of the area in the memory arrays and regularly stores the basic information. Radiation solidifying of inserted memory arrays is normally accomplished by actualizing incredibly expansive bit cells and keeping up a moderately high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption.In this paper, we propose a radiation-solidified static random access memory (SRAM) bitcell focused at low-voltage usefulness, while keeping up high soft-error robustness. The proposed 4T SRAM bit cell have a novel dual-driven seperated feedback mechanism to achieve high soft-error tolerance robust operation down to 300 mV.

show abstract

“…This results in a very fast and reliable, albeit power hungry operation.Low voltage operation in the "sub-threshold" or "near-threshold" regions have been found to be advantageous in dramatically reducing energy dissipation [16,18,19]. However, the power supply reduction is accompanied by a number of problems and significant challenges, especially in mass production designs [22][23][24][25][26]. The low voltage associated with frequency reduction is not suitable for all modes of operation, and an adaptive voltage control mechanism is required.…”

mentioning

confidence: 99%

0.45v and 18pA/MHz MCU SOC with advanced Adaptive Dynamic Voltage Control (ADVC)

Zangi¹,

Feldman²,

Shor

et al. 2017

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Self Cite

View full text Add to dashboard Cite

An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312 K-80 MHz. A number of unique low voltage digital libraries, comprising of approximately 300 logic cells and sequential elements, were used for the MCU SOC design. On-die silicon sensors were utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions, and also to resolve yield and life time problems, while operating at low voltages. A First Fail (FFail) mechanism, which can be digitally and linearly controlled with up to 8 bits, detects the failing SOC voltage at a given frequency. The core operates between 0.45-1.1 V volts with a direct battery connection for an input voltage of 1.6-3.6 V. Measurement results show that the peak energy efficiency is 18µW/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3-5× improved current/DMIPS (Dhrystone Million Instructions per second) compared to the next best chip. efficient) Systems on a Chips (SoC) that can support both minimum energy operation, and also reliably adapt their operating voltage to different environmental conditions is very challenging.Unfortunately, conventional SoCs, using supply voltages in the range of 0.9-1.8 V, are not suitable for IoT applications. In these SoCs, the "on" transistors operate in "super-threshold" region, far above the switching threshold of a transistor. In this region, the "Ion" current of a transistor is very strong, which results in a ratio of many orders of magnitude between the "Ion" and the "Ioff" (parasitic leakage) currents. This results in a very fast and reliable, albeit power hungry operation.Low voltage operation in the "sub-threshold" or "near-threshold" regions have been found to be advantageous in dramatically reducing energy dissipation [16,18,19]. However, the power supply reduction is accompanied by a number of problems and significant challenges, especially in mass production designs [22][23][24][25][26]. The low voltage associated with frequency reduction is not suitable for all modes of operation, and an adaptive voltage control mechanism is required. Lower supply voltages also mean lower noise margins, reduced yield, and increased vulnerability to process variations and temperature fluctuations [27][28][29][30][31][32]. The characteristics of semiconductor behavior in sub/near-threshold are not well represented by standard transistor models and are different from those in the super-threshold region, resulting in different sizing and ratio optimizations.The subthreshold current is exponentially dependent on the transistor's threshold voltage. Hence, process variations that substantially affect the threshold vol...

show abstract

Digital subthreshold logic design - motivation and challenges

Cited by 33 publications

References 10 publications

All-metallic electrically gated 2H-TaSe₂ thin-film switches and logic circuits

All-metallic electrically gated 2H-TaSe₂ thin-film switches and logic circuits

An Ultra Low Power Space Application based Radiation-Hardened Low Voltage 4T SRAM Bitcell

0.45v and 18pA/MHz MCU SOC with advanced Adaptive Dynamic Voltage Control (ADVC)

Contact Info

Product

Resources

About

Digital subthreshold logic design - motivation and challenges

Cited by 33 publications

References 10 publications

All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits

An Ultra Low Power Space Application based Radiation-Hardened Low Voltage 4T SRAM Bitcell

0.45v and 18pA/MHz MCU SOC with advanced Adaptive Dynamic Voltage Control (ADVC)

Contact Info

Product

Resources

About

All-metallic electrically gated 2H-TaSe₂ thin-film switches and logic circuits

All-metallic electrically gated 2H-TaSe₂ thin-film switches and logic circuits