Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

Abstract

In this paper we propose and analyze a Pulse-Output Digital-to-Frequency Converter (DFC) generating square waves, that uses a Digital-to-Time Converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system and we explore possibilities and limits of this approach in terms of cleanness of the output spectrum. Behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worstcase spur, that leads to a simple design equation. This is useful to determine the DTC requirements (number of bits, Integral Non-Linearity (INL)) given a certain Spurious-Free Dynamic Range (SFDR) target. We show that the maximum spur strength, in dBc, depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL and other impairments) and increases with the ratio by 6 dB per octave.

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

“…The main objective of this work is to systematically analyze these effects and present a multi-phase DPC circuit to mitigate them. Although our treatment of the subject targets DPC's usage in a certain category of high speed CDRs, the proposed techniques can be effective in other applications [7] as well.…”