Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells

An offset distribution modification technique of stochastic flash ADC

“…The improvement factor of the third-order non-linear distortion is ð1 À 6=e 2 Þ=ð1 þ 2=e 2 Þ % 0:148 (−16.6 dB). The linearization of the piecewise inverse Gaussian approximation in digital domain was proposed as a different approach [10]. However, it has no sensitivity enhancement …”

“…The proposed technique can relax significant input capacitance effect described in [10]. Even after using this modification of the PDF of the responding comparators, there remains non-linearity in the SF-ADC characteristics.…”

“…The minimum of effective-number-of-bits (ENOB) in input range was used so as to maximize as fitness function in this work. Differently from the linearization of the piecewise inverse Gaussian approximation [10], the RQ technique has tolerance for the assumption of Gaussian comparator offset distribution.…”

“…In this design, N comp ¼ 511 and k ¼ 9. To relax the timing requirement by pipelining [10,16], D-flip-flops are placed after the first, the fourth, the sixth, and the last adder stages, resulting in three sampling cycles of the latency. As this work focuses on the feasibility of the proposed SF-ADC, some digital blocks were not implemented on the integrated circuit.…”

“…This approach has led to the proposal of stochastic flash ADCs (SFADCs), which apply the statistical nature of comparator offsets to detect signals below the offset level thereby maintain good dynamic range even in fine-process devices with substantial mismatch [8,9,10]. This technique originates from a detection principle of small signal with noise, so-called stochastic resonance [11,12,13,14].…”