Direct Digital Frequency Synthesizers

Kroupa, Věnceslav F.

doi:10.1109/9780470544396

Cited by 134 publications

(49 citation statements)

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“…1 [13], uses an overflowing accumulator to produce a digital phase. This forms the address to a ROM lookup table of amplitude values that are then converted into an analogue output by a DAC [14]. The result is an output signal whose frequency is determined by the clock frequency and a user defined digital input to the accumulator.…”

Section: Conventional Ddfsmentioning

confidence: 99%

Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC

McEwan

Collins

2006

Analog Integr Circ Sig Process

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A non-linear interpolation based ROM-less Direct Digital Frequency Synthesisiser (DDFS) is more efficient than previous systems as each current cell in a non-linear DAC is used more effectively. This was achieved by forming an analogue voltage from a small linear DAC addressed by phase bits that are usually discarded. The analogue voltage was connected to a selected current source in a thermometer decoded non-linear DAC to allow nonlinear interpolation between the conventional, phase limited output levels. By increasing the number of phase bits the spurious free dynamic range (SFDR) was improved without increasing the size of the non-linear DAC. Modelling and simulation of the non-linear response of the differential switch based current cell revealed suitable parameters. The architecture of 64 current cells used a modified thermometer decoder and three-state switch in each current cell. Simulation and testing of 10 sample circuits demonstrated a robust DDFS with SFDR better than − 60 dBc and suitable for use in a wide range of instrumentation systems.

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Section: Conventional Ddfsmentioning

confidence: 99%

Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC

McEwan

Collins

2006

Analog Integr Circ Sig Process

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“…Two popular digital synthesizers focus on Direct Digital Synthesizer (DDS) [4] and FM synthesizers [5]. The crucial technique in DDS is the phase-amplitude conversion architecture [6].…”

Section: Introductionmentioning

confidence: 99%

FPGA implementation of a parameterized Fourier synthesizer

Yang

Wang

Clément

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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Abstract-Field-Programmable Gate Array (FPGA) offers advantages for many applications, particularly where missions are complex and time performance is critical. For small-production digital acoustic synthesizers, FPGA can achieve the abovementioned tighter system requirements with low total system costs on single chip. In this manuscript, a real-time acoustic synthesizer is implemented using Fourier series algorithm on Altera's Cyclone II FPGA chip. This work emphasizes systematic designs and parallel computations. The proposed system includes a flexible processor and a parallel parameterized acoustic module. On one hand, the Nios II embedded processor, which is relatively low-speed component, is used to generate commands and configure high-speed acoustic module parameters. On the other hand, acoustic module which should require high-speed components contains 4 parallel architectures to gain high-speed simultaneous calculus of 4 independent digital timbres. Every timbre is equivalent to 16 parallel high-precision harmonic channels with 0.3 % frequency error. Experimental results corroborate the fact that a single FPGA chip can achieve complex missions and attain real-time performances.

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“…One method consists of exploiting the quarter wave symmetry of the sine function to reduce by 4 the number of angles for which a sine amplitude is required [5]. Truncating the phase accumulator output is another common method, although it introduces spurious harmonics [6].…”

Section: Review Of Existing Workmentioning

confidence: 99%

“…This limits spurs due to phase truncation to approximately -72 dBc [6]. The two MSBs are used for quadrant symmetry [5]. The first MSB determines the sign of the output data.…”

Section: System Architecturementioning

confidence: 99%

A low power direct digital frequency synthesizer with 60 dBc spectral purity

Langlois¹,

Al-Khalili²

2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02

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We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ROM or multipliers are used, but an external DAC is required if an analog output is desired. Power consumption is 10 mW for a 100 MHz clock, which is significantly less than figures reported previously. System complexity is greatly reduced by using an efficient linear interpolation scheme to approximate a sinusoid function. This has resulted in silicon area utilization of 0.011 mm 2 . The design would be suitable as an IP core in a low power digital RF transceiver ASIC.

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Direct Digital Frequency Synthesizers

Cited by 134 publications

References 0 publications

Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC

Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC

FPGA implementation of a parameterized Fourier synthesizer

A low power direct digital frequency synthesizer with 60 dBc spectral purity

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