2005
DOI: 10.1007/b117054
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Direct Transistor-level Layout for Digital Blocks

Abstract: Chapter 3 Global Placement 35 Chapter 4 Detailed Placement And Layout Results 49 vi Direct Transistor-Level Layout for Digital Blocks 75 77 78 79 80 81 85 88 89 90 91 91 92 95 96 97 101 Chapter 5 Timing-Driven Placement 77 Chapter 6 Conclusion 103 Appendix 107 Bibliography 115 Index 123 Contents vii PRAKASH GOPALAKRISHNAN NEOLINEAR, INC.

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