Direct visualization of anomalous-phosphorus diffusion in failure-bit gates of SRAM-load pMOSFETs with high-resolution scanning spreading resistance microscopy

Abstract

In this study, we directly observed fail bits of pMOS with V th variations in SRAM by both SSRM and a nanoprober, clarified that the failure is originated from the phosphorus anomalous diffusion into the pMOS gate bottom. We succeeded in observing the pn-junction boundary within a thin SRAM poly-Si gate with the size of less than 60 nm. The gate-phosphorus doping and STI geometry influence on pn boundary is investigated systematically. A significant improvement in process margin is achieved with controlling of the phosphorous-anomalous diffusion.

Effect of Oxygen Plasma Surface Pretreatment on Silicon Based Dielectrics and Conductor Substrate

“…This may cause SRAM function failed with threshold voltage (V th ) variation of pMOS. 12 The common practice is shifting P-N boundary during the precondition without prejudice to nMOS as illustrated in Fig. 11.…”