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In this study, we directly observed fail bits of pMOS with V th variations in SRAM by both SSRM and a nanoprober, clarified that the failure is originated from the phosphorus anomalous diffusion into the pMOS gate bottom. We succeeded in observing the pn-junction boundary within a thin SRAM poly-Si gate with the size of less than 60 nm. The gate-phosphorus doping and STI geometry influence on pn boundary is investigated systematically. A significant improvement in process margin is achieved with controlling of the phosphorous-anomalous diffusion.

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