Applications of site-specific scanning spreading resistance microscopy (SSRM) to failure analysis of production lines

Three-Dimensional Nanoscale Mapping of State-of-the-Art Field-Effect Transistors (FinFETs)

“…The tolerance in fin width has been calculated to about 1 nm for industry acceptable variability in electrical parameters for 20 nm finFETs and a tolerance of 10–15% for variations in gate length (Shiying & Bokor, 2003). Further, diffusion of dopants into the Si channel can cause large changes in the electronic density, known as random density fluctuations; these are an important part of current experimental and computational studies (Pei et al, 2002; Bernstein et al, 2006; Baravelli et al, 2008; Wang et al, 2011). A failed device could hence differ from a working device based on small structural or concentration fluctuations.…”

“…With the current production technology node at 14 nm (based on fin width), identifying and understanding individual finFETs is a burgeoning field. Defects in finFETs are currently identified using electrical, optical, or thermal techniques such as soft defect localization using a scanning optical microscope (Bruce et al, 2003;Phang et al, 2004), infrared (IR)-based techniques, due to Si being transparent to IR wavelengths (Nikawa et al, 1999;Phang et al, 2004) and scanning spread resistance microscopy (Zhang et al, 2007;Hayase et al, 2012). Although these techniques can tell the pass or fail state of each transistor and a localized region where the FETs are good or bad, the relationship between device failure and structural or concentration anomalies is still missing.…”

“…Although these techniques can tell the pass or fail state of each transistor and a localized region where the FETs are good or bad, the relationship between device failure and structural or concentration anomalies is still missing. At best these techniques can provide a spatial resolution of~50 nm (Nikawa et al, 1999;Bruce et al, 2003;Phang et al, 2004;Zhang et al, 2007;Hayase et al, 2012).…”

“…Soft defects occurring due to dielectric breakdown, process variations, and resistive interconnects are more often attributed to structural defects at the atomic level. Specifically, line-edge roughness and fin thickness variations can affect the threshold voltage and sub threshold slope (Pei et al, 2002; Baravelli et al, 2008), both important electrical parameters for low power devices. Variations in the oxide layer thickness can give rise to larger tunneling currents (Bernstein et al, 2006), while discrete impurity atoms in the channel can significantly affect the current density in the channel (Wang et al, 2011).…”