Discharge mechanisms modeling in LPCVD silicon nanocrystals usingC–Vand capacitance transient techniques†

Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

“…6 The dominant mechanism is thus charging of the MOS dielectric in the presence of large number of electrons in Au NCs, and therefore, effect of the traps and defects can be ignored in most of such cases. 7 Interestingly, a new phenomenon of smearing out of the C-V curve is observed in the case of dual NC layer indicating generation of interface traps. When the MOS structure is biased for accumulation, the NCs in the layer near the gate are positively charged whereas those near the Si substrate are negatively charged.…”

Silicon Nanocrystal Flash Memory

“…A logarithmic law can be found at the initial time (up to 10 4 s). This suggests that the tunneling probability varies with time, as a constant probability would give an exponential dependence [69]. That is to say that the electric field across the tunneling barrier is a function of time since the tunneling probability depends on the electric field [70].…”

Charge retention characteristics of silicon nanocrystal layers by ultrahigh vacuum atomic force microscopy

“…The charge retention characteristics directly observed in nanoscale are consistent with previous data obtained by capacitancevoltage measurements on nanocrystal floating gate MOS capacitors. 8,15,16 In theory, holes having much better retention characteristics than electrons can be explained by the difference in tunneling barrier heights, 3.1 and 4.7 eV for electrons and holes, respectively. The retention times are also influenced by carrier effective mass in tunneling.…”